SLVSH03 December   2023 DRV8234

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Operating Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Summary of Features
      3. 7.3.3 Bridge Control
      4. 7.3.4 Current Sense and Regulation (IPROPI)
        1. 7.3.4.1 Current Sensing
        2. 7.3.4.2 Current Regulation
          1. 7.3.4.2.1 Fixed Off-Time Current Regulation
          2. 7.3.4.2.2 Cycle-By-Cycle Current Regulation
      5. 7.3.5 Stall Detection
      6. 7.3.6 Ripple Counting
        1. 7.3.6.1 Ripple Counting Parameters
          1. 7.3.6.1.1  Motor Resistance Inverse
          2. 7.3.6.1.2  Motor Resistance Inverse Scale
          3. 7.3.6.1.3  KMC Scaling Factor
          4. 7.3.6.1.4  KMC
          5. 7.3.6.1.5  Filter Damping Constant
          6. 7.3.6.1.6  Filter Input Scaling Factor
          7. 7.3.6.1.7  Ripple Count Threshold
          8. 7.3.6.1.8  Ripple Count Threshold Scale
          9. 7.3.6.1.9  T_MECH_FLT
          10. 7.3.6.1.10 VSNS_SEL
          11. 7.3.6.1.11 Error Correction
            1. 7.3.6.1.11.1 EC_FALSE_PER
            2. 7.3.6.1.11.2 EC_MISS_PER
        2. 7.3.6.2 RC_OUT Output
        3. 7.3.6.3 Ripple Counting with nFAULT
      7. 7.3.7 Motor Voltage and Speed Regulation
        1. 7.3.7.1 Internal Bridge Control
        2. 7.3.7.2 Setting Speed/Voltage Regulation Parameters
          1. 7.3.7.2.1 Speed and Voltage Set
          2. 7.3.7.2.2 Speed Scaling Factor
        3. 7.3.7.3 Soft-Start and Soft-Stop
          1. 7.3.7.3.1 TINRUSH
      8. 7.3.8 Protection Circuits
        1. 7.3.8.1 Overcurrent Protection (OCP)
        2. 7.3.8.2 Thermal Shutdown (TSD)
        3. 7.3.8.3 VM Undervoltage Lockout (VM UVLO)
        4. 7.3.8.4 Overvoltage Protection (OVP)
        5. 7.3.8.5 nFAULT Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Low-Power Sleep Mode
      3. 7.4.3 Fault Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Communication
        1. 7.5.1.1 I2C Write
        2. 7.5.1.2 I2C Read
    6. 7.6 Register Map
      1. 7.6.1 DRV8234_STATUS Registers
      2. 7.6.2 DRV8234_CONFIG Registers
      3. 7.6.3 DRV8234_CTRL Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Brushed DC Motor
      1. 8.2.1 Design Requirements
      2. 8.2.2 Stall Detection
        1. 8.2.2.1 Application Description
          1. 8.2.2.1.1 Stall Detection Timing
          2. 8.2.2.1.2 Hardware Stall Threshold Selection
      3. 8.2.3 Ripple Counting Application
        1. 8.2.3.1 Tuning Ripple Counting Parameters
          1. 8.2.3.1.1 Resistance Parameters
          2. 8.2.3.1.2 KMC and KMC_SCALE
            1. 8.2.3.1.2.1 Case I
            2. 8.2.3.1.2.2 Case II
              1. 8.2.3.1.2.2.1 Method 1: Tuning from Scratch
                1. 8.2.3.1.2.2.1.1 Tuning KMC_SCALE
                2. 8.2.3.1.2.2.1.2 Tuning KMC
              2. 8.2.3.1.2.2.2 Method 2: Using the Proportionality factor
                1. 8.2.3.1.2.2.2.1 Working Example
          3. 8.2.3.1.3 Advanced Parameters
            1. 8.2.3.1.3.1 Filter Constants
              1. 8.2.3.1.3.1.1 FLT_GAIN_SEL
              2. 8.2.3.1.3.1.2 FLT_K
            2. 8.2.3.1.3.2 T_MECH_FLT
            3. 8.2.3.1.3.3 VSNS_SEL
            4. 8.2.3.1.3.4 Additional Error Corrector Parameters
              1. 8.2.3.1.3.4.1 EC_FALSE_PER
              2. 8.2.3.1.3.4.2 EC_MISS_PER
      4. 8.2.4 Motor Voltage
      5. 8.2.5 Motor Current
      6. 8.2.6 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.3 DRV8234_CTRL Registers

Table 7-43 lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in Table 7-43 should be considered as reserved locations and the register contents should not be modified.

Table 7-43 DRV8234_CTRL Registers
OffsetAcronymRegister NameSection
EhREG_CTRL0Regulation control registers (1/3).Section 7.6.3.1
FhREG_CTRL1Regulation control registers (2/3).Section 7.6.3.2
10hREG_CTRL2Regulation control registers (3/3).Section 7.6.3.3
11hRC_CTRL0Ripple Counting Control Registers - (1/9).Section 7.6.3.4
12hRC_CTRL1Ripple Counting Control Registers - (2/9).Section 7.6.3.5
13hRC_CTRL2Ripple Counting Control Registers - (3/9).Section 7.6.3.6
14hRC_CTRL3Ripple Counting Control Registers - (4/9).Section 7.6.3.7
15hRC_CTRL4Ripple Counting Control Registers - (5/9).Section 7.6.3.8
16hRC_CTRL5Ripple Counting Control Registers - (6/9).Section 7.6.3.9
17hRC_CTRL6Ripple Counting Control Registers - (7/9).Section 7.6.3.10
18hRC_CTRL7Ripple Counting Control Registers - (8/9).Section 7.6.3.11
19hRC_CTRL8Ripple Counting Control Registers - (9/9).Section 7.6.3.12

Complex bit access types are encoded to fit into small table cells. Table 7-44 shows the codes that are used for access types in this section.

Table 7-44 DRV8234_CTRL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.3.1 REG_CTRL0 Register (Offset = Eh) [Reset = 27h]

REG_CTRL0 is shown in Table 7-45.

Return to the Summary Table.

Set features like Soft Start/Stop, speed scaling factor, etc.

Table 7-45 REG_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RSVDR0h Reserved.
5EN_SSR/W1h Used to enable/disable soft start/stop.
1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time.
0b: Soft-start/stop feature is disabled.
Refer to DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. Revision History DATE REVISION NOTES January 2023 * Initial Release Revision History DATE REVISION NOTES January 2023 * Initial Release DATE REVISION NOTES January 2023 * Initial Release DATE REVISION NOTES January 2023 * Initial Release DATE REVISION NOTES January 2023 * Initial Release DATE REVISION NOTES DATE REVISION NOTES DATEREVISIONNOTES January 2023 * Initial Release January 2023 * Initial Release January 2023 January 2023*Initial Release IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation.
00b: Fixed Off-Time Current Regulation.
01b: Cycle-By-Cycle Current Regulation.
10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b.
11b: Motor voltage is regulated.
Refer to DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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IMPORTANT NOTICE IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated for further explanation.
2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b).
0b: PWM frequency is set to 50kHz.
1b: PWM frequency is set to 25kHz.
1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed.
00b: 16
01b: 32
10b: 64
11b: 128
Refer to DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. 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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. 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7.6.3.2 REG_CTRL1 Register (Offset = Fh) [Reset = FFh]

REG_CTRL1 is shown in Table 7-46.

Return to the Summary Table.

Set the target motor voltage and speed.

Table 7-46 REG_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed.
A detailed explanation is provided in DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. 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IMPORTANT NOTICE IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated.

7.6.3.3 REG_CTRL2 Register (Offset = 10h) [Reset = 00h]

REG_CTRL2 is shown in Table 7-47.

Return to the Summary Table.

Set the duty cycle and cut-off frequency for output voltage filtering.

Table 7-47 REG_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering.
00b: 250Hz
01b: 500Hz
10b: 750Hz
11b: 1000Hz
For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient.
5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b).

7.6.3.4 RC_CTRL0 Register (Offset = 11h) [Reset = 88h]

RC_CTRL0 is shown in Table 7-48.

Return to the Summary Table.

Set various functions for RC including enable/disable.

Table 7-48 RC_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
7EN_RCR/W1h Enable/Disable Ripple Counting.
0b: Disable
1b: Enable
6DIS_ECR/W0h Enable/Disable the Error Correction module.
0b: Error Correction is enabled.
1b: Error Correction is disabled.
Please note that this is different from the EC_PULSE_DIS described earlier.
5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold.
1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold.
4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are:
00b: 2
01b: 4
10b: 8
11b: 16
Refer to DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows:
X00b: 4 A
X01b: 2 A
X10b: 1 A
X11b: 0.5 A

7.6.3.5 RC_CTRL1 Register (Offset = 12h) [Reset = FFh]

RC_CTRL1 is shown in Table 7-49.

Return to the Summary Table.

Threshold for ripple counting.

Table 7-49 RC_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register.
Threshold level to compare against the RC_CNT based on the expected time of motor actuation.
Ripple counting threshold = RC_THR x RC_THR_SCALE

7.6.3.6 RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh]

RC_CTRL2 is shown in Table 7-50.

Return to the Summary Table.

Set values of various scaling parameters.

Table 7-50 RC_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter.
00b: INV_R_SCALE = 2
01b: INV_R_SCALE = 64
10b: INV_R_SCALE = 1024
11b: INV_R_SCALE = 8192
Refer to DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. 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IMPORTANT NOTICE IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated for further explanation.
5-4KMC_SCALER/W3h Scaling factor for KMC parameter.
00b: KMC_SCALE = 24 x 28
01b: KMC_SCALE = 24 x 29
10b: KMC_SCALE = 24 x 212
11b: KMC_SCALE = 24 x 213
Refer to DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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3-2RC_THR_SCALER/W3h Scaling factor for RC_THR.
00b: RC_THR_SCALE = 2
01b: RC_THR_SCALE = 8
10b: RC_THR_SCALE = 16
11b: RC_THR_SCALE = 64
1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register.
Threshold level to compare against RC_CNT based on the expected time of motor actuation.
Ripple counting threshold = RC_THR x RC_THR_SCALE

7.6.3.7 RC_CTRL3 Register (Offset = 14h) [Reset = 00h]

RC_CTRL3 is shown in Table 7-51.

Return to the Summary Table.

Set the INV_R parameter.

Table 7-51 RC_CTRL3 Register Field Descriptions
BitFieldTypeResetDescription
7-0INV_RR/W0h User input based on motor coil resistance.
INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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7.6.3.8 RC_CTRL4 Register (Offset = 15h) [Reset = 00h]

RC_CTRL4 is shown in Table 7-52.

Return to the Summary Table.

Set the KMC parameter.

Table 7-52 RC_CTRL4 Register Field Descriptions
BitFieldTypeResetDescription
7-0KMCR/W0h Represents a proportional value of the motor back emf constant.
KMC = (KV) / NR)*KMC_SCALE.
Refer to DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. 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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. 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7.6.3.9 RC_CTRL5 Register (Offset = 16h) [Reset = 00h]

RC_CTRL5 is shown in Table 7-53.

Return to the Summary Table.

Set the filter damping constant.

Table 7-53 RC_CTRL5 Register Field Descriptions
BitFieldTypeResetDescription
7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter.
Recommended value is the default value: 6d.
Refer to DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. 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3-0RSVDR0h Reserved

7.6.3.10 RC_CTRL6 Register (Offset = 17h) [Reset = 45h]

RC_CTRL6 is shown in Table 7-54.

Return to the Summary Table.

Disable the Error Correction pulses for Ripple Counting.

Table 7-54 RC_CTRL6 Register Field Descriptions
BitFieldTypeResetDescription
7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled.
1b: Error correction will stop giving pulses under certain conditions described in DRV8234 2-A Brushed DC Motor Driver with Stall Detection, Ripple Counting and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features Features Applications Applications Description Description Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics I2C Timing Requirements I2C Timing Requirements Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description External Components External Components Summary of Features Summary of Features Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing Current Sensing Current Regulation Current Regulation Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current Regulation Stall Detection Stall Detection Ripple Counting Ripple Counting Ripple Counting Parameters Ripple Counting Parameters Motor Resistance Inverse Motor Resistance Inverse Motor Resistance Inverse Scale Motor Resistance Inverse Scale KMC Scaling Factor KMC Scaling Factor KMC KMC Filter Damping Constant Filter Damping Constant Filter Input Scaling Factor Filter Input Scaling Factor Ripple Count Threshold Ripple Count Threshold Ripple Count Threshold Scale Ripple Count Threshold Scale T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Error Correction Error Correction EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER RC_OUT Output RC_OUT Output Ripple Counting with nFAULT Ripple Counting with nFAULT Motor Voltage and Speed Regulation Motor Voltage and Speed Regulation Internal Bridge Control Internal Bridge Control Setting Speed/Voltage Regulation Parameters Setting Speed/Voltage Regulation Parameters Speed and Voltage Set Speed and Voltage Set Speed Scaling Factor Speed Scaling Factor Soft-Start and Soft-Stop Soft-Start and Soft-Stop TINRUSH TINRUSH Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (VM UVLO) VM Undervoltage Lockout (VM UVLO) Overvoltage Protection (OVP) Overvoltage Protection (OVP) nFAULT Output nFAULT Output Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Programming Programming I2C Communication I2C Communication I2C Write I2C Write I2C Read I2C Read Register Map Register Map DRV8234_STATUS Registers DRV8234_STATUS Registers DRV8234_CONFIG Registers DRV8234_CONFIG Registers DRV8234_CTRL Registers DRV8234_CTRL Registers Application and Implementation Application and Implementation Application Information Application Information Typical Application: Brushed DC Motor Typical Application: Brushed DC Motor Design Requirements Design Requirements Stall Detection Stall Detection Application Description Application Description Stall Detection Timing Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Ripple Counting Application Ripple Counting Application Tuning Ripple Counting Parameters Tuning Ripple Counting Parameters Resistance Parameters Resistance Parameters KMC and KMC_SCALE KMC and KMC_SCALE Case I Case I Case II Case II Method 1: Tuning from Scratch Method 1: Tuning from Scratch Tuning KMC_SCALE Tuning KMC_SCALE Tuning KMC Tuning KMC Method 2: Using the Proportionality factor Method 2: Using the Proportionality factor Working Example Working Example Advanced Parameters Advanced Parameters Filter Constants Filter Constants FLT_GAIN_SEL FLT_GAIN_SEL FLT_K FLT_K T_MECH_FLT T_MECH_FLT VSNS_SEL VSNS_SEL Additional Error Corrector Parameters Additional Error Corrector Parameters EC_FALSE_PER EC_FALSE_PER EC_MISS_PER EC_MISS_PER Motor Voltage Motor Voltage Motor Current Motor Current Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation DRV8234 2-A Brushed DC Motor Driver with Ripple Counting, Stall Detection, and Speed Regulation Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) Features N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Soft-Start and Stop feature for inrush current protection 600-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 3.7-A Peak, 2-A RMS PWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Supports 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Internal charge pump with 100% duty cycle Long battery life with low-power sleep mode < 1 μA maximum sleep current Small package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm Integrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) N-channel H-bridge brushed DC motor driver 4.5-V to 38-V operating supply voltage range4.5-V to 38-V Ripple counting feature for: On-chip Speed and Position detection Integrated Voltage and Speed regulation Ripple counting On-chip Speed and Position detection Integrated Voltage and Speed regulation On-chip Speed and Position detection Speed and Position detectionIntegrated Voltage and Speed regulation VoltageSpeed regulation Soft-Start and Stop feature for inrush current protectionSoft-Start and Stop 600-mΩ RDS(on) (High-Side + Low-Side)600-mΩDS(on)High output current capability: 3.7-A Peak, 2-A RMSPWM with I2C control interface Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode 2 Configuration and diagnostics on I2C registers Multi-follower operation support Supports standard and fast I2C mode Configuration and diagnostics on I2C registers2Multi-follower operation supportSupports standard and fast I2C mode2Supports 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)Internal charge pump with 100% duty cycleLong battery life with low-power sleep mode < 1 μA maximum sleep current < 1 μA maximum sleep current < 1 μA maximum sleep currentSmall package and footprint 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mm 16-Pin WQFN with PowerPAD, 3 × 3 mmPowerPADIntegrated protection features VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO) Overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection Overvoltage protection (OVP) VM undervoltage lockout (UVLO)Overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection Stall detectionOvervoltage protection (OVP) Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Applications Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Vacuum Robots Washers and Dryers Coffee Machines POS Printers Electronic Hospital bed and bed control Fitness Machine Printers Printers Vacuum Robots Vacuum Robots Washers and Dryers Washers and Dryers Coffee Machines Coffee Machines POS Printers POS Printers Electronic Hospital bed and bed control Electronic Hospital bed and bed control Fitness Machine Fitness Machine Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Description The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The DRV8234 is a high-performance integrated H-bridge motor driver with integrated speed and position detection using ripple counting along with additional features like motor speed and voltage regulation, stall detection, current sense output, current regulation, and protection circuitry. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. The integrated ripple counting algorithm counts the number of ripples in the motor current to determine motor relative position and speed eliminating the potential need for encoders, hall sensors, or optical sensors. This reduces board space and design complexity, and saves on overall system cost. Integrated speed regulation is used to maintain constant motor speed over varying input supply voltages which minimizes current consumption and saves power over time. This is critical in applications that have different loading conditions or rely on battery power for operation where the input voltage is not constant. Soft-start and stop allows for a controlled turn-on and turn-off time, reducing large inrush currents to protect the motor windings from damage, thereby increasing system reliability and longevity. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The device supports sensorless motor stall detection and reporting to microcontroller. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm Device Information PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBER PACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D BODY SIZE (NOM) PART NUMBERPACKAGE#GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431DBODY SIZE (NOM) DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234 WQFN (16) 3.00 mm × 3.00 mm DRV8234WQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Simplified Schematic Simplified Schematic #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D #GUID-48875F2A-CA7C-474A-ADF7-1A9B8C6B03F6/GUID-EB963CA2-6D1E-427C-B790-86A2DF07431D Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Device Comparison Table Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part Number Package Supply VM (V) RDS(ON) (mΩ) Current Capacity (RMS) Ripple Counting Speed Regulation Stall Detection Package Size Part NumberPackageSupply VM (V)RDS(ON) (mΩ)DS(ON) Current Capacity (RMS)Ripple CountingSpeed RegulationStall DetectionPackage Size DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8214 RTE 1.65 to 11 240 2 A Yes Yes Yes 3 mm × 3 mm DRV8214RTE1.65 to 112402 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8234 RTE 4.5 to 38 600 2 A Yes Yes Yes 3 mm × 3 mm DRV8234RTE4.5 to 386002 A Yes Yes Yes Yes Yes Yes3 mm × 3 mm DRV8215 RTE 1.65 to 11 240 2 A No Yes Yes 3 mm × 3 mm DRV8215RTE1.65 to 112402 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8235 RTE 4.5 to 38 600 2 A No Yes Yes 3 mm × 3 mm DRV8235RTE4.5 to 386002 ANo Yes Yes Yes Yes3 mm × 3 mm DRV8213 RTE 1.65 to 11 240 2 A No No Yes 3 mm × 3 mm DRV8213 DRV8213RTE1.65 to 112402 ANoNo Yes Yes3 mm × 3 mm DRV8213 DSG 1.65 to 11 240 2 A No No No 2 mm × 2 mm DRV8213 DRV8213DSG1.65 to 112402 ANoNoNo2 mm × 2 mm Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output Pin Configuration and Functions RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package 16-Pin WQFN Top View RTE Package16-Pin WQFNTop View Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION NAME RTE PIN TYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 DESCRIPTION PINTYPE#GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71 #GUID-41D31175-BEC0-4D97-999C-D3E93E4B2E68/GUID-638DAEF5-A3C0-4085-ADD4-ECE6E76D0D71DESCRIPTION NAME RTE NAMERTE IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A0 10 I I2C base address select pin. Tri-level input. nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SCL 15 I I2C clock signal. VREF 16 I Analog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. IPROPI 1 PWR Analog current output proportional to load current. Connect a resistor from IPROPI to ground. IPROPI1PWRAnalog current output proportional to load current. Connect a resistor from IPROPI to ground. RSVD 2 — Reserved. Leave this pin unconnected. RSVD 2 2—Reserved. Leave this pin unconnected. RC_OUT 3 OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. RC_OUT 3 3OD Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal. Output of Ripple Counting algorithm. Can be programmed by I2C to output pulse train or logic level signal.2 nFAULT 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. nFAULT 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. VM 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM5PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. OUT1 6 O H-bridge output. Connect directly to the motor. OUT16OH-bridge output. Connect directly to the motor. GND 7 PWR Device ground. Connect to system ground. GND7PWRDevice ground. Connect to system ground. OUT2 8 O H-bridge output. Connect directly to the motor. OUT28OH-bridge output. Connect directly to the motor. A1 9 I I2C base address select pin. Tri-level input. A1 A1 9 9II2C base address select pin. Tri-level input.2 A0 10 I I2C base address select pin. Tri-level input. A0 A0 10 10 I II2C base address select pin. Tri-level input.2 nSLEEP 11 I Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. nSLEEP 11 11 I ISleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. Internal pulldown resistor. PH/IN2 12 I Controls the H-bridge output. Has internal pulldown. PH/IN212IControls the H-bridge output. Has internal pulldown. EN/IN1 13 I Controls the H-bridge output. Has internal pulldown. EN/IN113IControls the H-bridge output. Has internal pulldown. SDA 14 I I2C data signal. The SDA pin requires a pullup resistor. SDA SDA 14 14 I I I2C data signal. The SDA pin requires a pullup resistor. I2C data signal. The SDA pin requires a pullup resistor.2 SCL 15 I I2C clock signal. SCL15I I2C clock signal. I2C clock signal.2 VREF 16 I Analog input to set current regulation and stall detection level. VREF16IAnalog input to set current regulation and stall detection level. PAD — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD——Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. I = Input, O = Output, PWR = Power, OD = Open-Drain Output I = Input, O = Output, PWR = Power, OD = Open-Drain Output Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314627/MD_ABSMAX_FOOTER1_SF1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 40 V Power supply transient voltage ramp VM 0 2 V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 40 V Power supply pin voltageVM-0.540V Power supply transient voltage ramp VM 0 2 V/µs Power supply transient voltage rampVM02V/µs Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V Logic pin voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP-0.35.75V Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V Open-drain output pin voltagenFAULT, RC_OUT-0.35.75V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER1_SF1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314628/MD_ESDRATINGS_COMMERCIAL_FOOTER2_SF1±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage VM 4.5 38 V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V fPWM PWM frequency INx 0 200 kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.3 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage VM 4.5 38 V VVM VMPower supply voltageVM4.538V VIN Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP 0 5.5 V VIN INLogic input voltageIN1, IN2, A1, A0, SDA, SCL, nSLEEP 05.5V fPWM PWM frequency INx 0 200 kHz fPWM PWMPWM frequencyINx0200kHz VOD Open drain pullup voltage nFAULT, RC_OUT 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, RC_OUT05.5V IOD Open drain output current nFAULT, RC_OUT 0 5 mA IOD ODOpen drain output currentnFAULT, RC_OUT05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 Peak output current OUTx 0 3.7 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314629/MD_ROC_FOOTER1_SF1_SF2_SF1_SF1Peak output currentOUTx03.7A IIPROPI Current sense output current IPROPI 0 3 mA IIPROPI IPROPICurrent sense output currentIPROPI03mA VVREF Current limit reference voltage VREF 0 3.3 V VVREF VREFCurrent limit reference voltageVREF03.3V TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT RTE (WQFN) 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000314630/MD_THERMAL_2PKG_FOOTER1_SF1DEVICEUNIT RTE (WQFN) RTE (WQFN) 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJA Junction-to-ambient thermal resistance 47.8 °C/W RθJA θJA Junction-to-ambient thermal resistance47.8°C/W RθJC(top) Junction-to-case (top) thermal resistance 48.2 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance48.2°C/W RθJB Junction-to-board thermal resistance 22.4 °C/W RθJB θJBJunction-to-board thermal resistance22.4°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 22.4 °C/W ΨJB JBJunction-to-board characterization parameter22.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance8.6°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C Electrical Characteristics 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C 4.5 V ≤ VVM ≤ 38 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical values are at TJ = 27°C, VVM = 24 V.VMJJVM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIH Input logic high voltage 1.5 5.5 V VHYS Input hysteresis 160 mV VHYS Input hysterisis nSLEEP pin 60 IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VI = 5 V 33 100 µA RPD Input pulldown resistance, INx To GND 100 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIH Tri-level input logic high voltage 2.7 5.5 V RTPD Tri-level pulldown resistance to GND 200 kΩ ITPU Tri-level pullup current to 3.3 V 10 µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 3.3 V -1 1 µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs CB SDA capacitive load for each bus line 400 pF DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tPD Input to output propagation delay Input to OUTx 650 ns tDEAD Output dead time 200 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V AIPROPI Current scaling factor 1500 µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % tOFF Current regulation off time 20 µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tINRUSH Inrush time blanking for stall detection 5 6716 ms Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V Supply falling 4.05 4.2 4.35 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_OFF Overvoltage protection turn-off time 250 µs IOCP Overcurrent protection trip point 3.7 A tOCP Overcurrent protection deglitch time 2 µs tRETRY Retry time 1.7 ms TTSD Thermal shutdown temperature 150 175 °C THYS Thermal shutdown hysteresis 40 °C POWER SUPPLIES (VM) POWER SUPPLIES (VM) IVMQ VM sleep mode current nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 0.1 1 µA IVMQ VMQVM sleep mode currentnSLEEP = 0 V, VVM = 24 V, TJ = 27°CVMJ0.11µA IVM VM active mode current nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 3.5 4 mA IVM VMVM active mode currentnSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 VVM3.54mA tWAKE Turnon time nSLEEP = 1 to I2C ready 410 μs tWAKE WAKETurnon timenSLEEP = 1 to I2C ready2410μs LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) LOGIC-LEVEL INPUTS (IN1, IN2, SDA, SCL, nSLEEP) VIL Input logic low voltage 0 0.5 V VIL ILInput logic low voltage00.5V VIH Input logic high voltage 1.5 5.5 V VIH IHInput logic high voltage1.55.5V VHYS Input hysteresis 160 mV VHYS HYSInput hysteresis160mV VHYS Input hysterisis nSLEEP pin 60 VHYS HYSInput hysterisisnSLEEP pin60 IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VI = 5 V 33 100 µA IIH IHInput logic high currentVI = 5 VI33100µA RPD Input pulldown resistance, INx To GND 100 kΩ RPD PDInput pulldown resistance, INxTo GND100kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (A1, A0) TRI-LEVEL INPUTS (A1, A0) VTIL Tri-level input logic low voltage 0 0.6 V VTIL TILTri-level input logic low voltage00.6V VTIHZ Tri-level input Hi-Z voltage 1.8 2 2.2 V VTIHZ TIHZTri-level input Hi-Z voltage1.822.2V VTIH Tri-level input logic high voltage 2.7 5.5 V VTIH TIHTri-level input logic high voltage2.75.5V RTPD Tri-level pulldown resistance to GND 200 kΩ RTPD TPDTri-level pulldown resistanceto GND200kΩ ITPU Tri-level pullup current to 3.3 V 10 µA ITPU TPUTri-level pullup currentto 3.3 V10µA OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) OPEN-DRAIN OUTPUTS (nFAULT, RC_OUT, SDA) VOL Output logic low voltage IOD = 5 mA 0.3 V VOL OLOutput logic low voltageIOD = 5 mAOD0.3V IOZ Output logic high current VOD = 3.3 V -1 1 µA IOZ OZOutput logic high currentVOD = 3.3 VOD-11µA tPW_RC RC_OUT pulse width 30 50 70 µs tPW_RC PW_RCRC_OUT pulse width305070µs tPW_nFAULT nFAULT low pulse width RC Count overflow, RC_REP = 11b 30 50 70 µs tPW_nFAULT PW_nFAULTnFAULT low pulse widthRC Count overflow, RC_REP = 11b305070µs CB SDA capacitive load for each bus line 400 pF CB BSDA capacitive load for each bus line400pF DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 A; TJ = 150 °COUTxJ500600mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 25 °C 300 360 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 25 °COUTxJ300360mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 125 °C 450 540 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 125 °COUTxJ450540mΩ RDS(ON)_LS Low-side MOSFET on resistance IOUTx = -1 A; TJ = 150 °C 500 600 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistanceIOUTx = -1 A; TJ = 150 °COUTxJ500600mΩ VSD Body diode forward voltage IOUTx = -1 A 0.8 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.8V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 200 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM200ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 140 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM140ns tPD Input to output propagation delay Input to OUTx 650 ns tPD PDInput to output propagation delayInput to OUTx650ns tDEAD Output dead time 200 ns tDEAD DEADOutput dead time200ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage INT_VREF = 1b 2.88 3 3.12 V VREF_INT REF_INTInternal reference voltageINT_VREF = 1b2.8833.12V AIPROPI Current scaling factor 1500 µA/A AIPROPI IPROPICurrent scaling factor1500µA/A AERR Current mirror total error IOUT = 0.1 A, VVM ≥ 5.5 V -10 10 % AERR ERRCurrent mirror total errorIOUT = 0.1 A, VVM ≥ 5.5 VOUTVM-1010% AERR Current mirror total error 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V -7 7 % AERR ERRCurrent mirror total error0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 VOUTVM-77% AERR Current mirror total error IOUT ≥ 0.5 A, VVM ≥ 5.5 V -5 5 % AERR ERRCurrent mirror total errorIOUT ≥ 0.5 A, VVM ≥ 5.5 VOUTVM-55% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current sense blanking time TBLANK = 0b 1.8 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 0b1.8µs tBLANK Current sense blanking time TBLANK = 1b 1 µs tBLANK BLANKCurrent sense blanking timeTBLANK = 1b1µs tDEG Current regulation and stall detection deglitch time TDEG = 0b 2 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 0b2µs tDEG Current regulation and stall detection deglitch time TDEG = 1b 1 µs tDEG DEGCurrent regulation and stall detection deglitch timeTDEG = 1b1µs tINRUSH Inrush time blanking for stall detection 5 6716 ms tINRUSH INRUSHInrush time blanking for stall detection56716ms Voltage regulation Voltage regulation ΔVLINE Line regulation 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A ±2% ΔVLINE LINELine regulation5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 AVMOUTOUT±2% ΔVLOAD Load regulation VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A ±1% ΔVLOAD LOADLoad regulationVVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 AVMOUTOUT±1% PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO) Supply rising 4.15 4.3 4.45 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO)Supply rising4.154.34.45V Supply falling 4.05 4.2 4.35 V Supply falling4.054.24.35V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 100 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold100mV tUVLO Supply undervoltage deglitch time VVM falling to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling to OUTx disabledVM10µs VRST VM UVLO reset VM falling, device reset, no I2C communications 3.9 V VRST RSTVM UVLO resetVM falling, device reset, no I2C communications23.9V VOVP_TH Overvoltage protection threshold VOUT - VVM 200 mV VOVP_TH OVP_THOvervoltage protection thresholdVOUT - VVM OUTVM200mV tOVP_ON Overvoltage protection turn-on time 10 µs tOVP_ON OVP_ONOvervoltage protection turn-on time10µs tOVP_OFF Overvoltage protection turn-off time 250 µs tOVP_OFF OVP_OFFOvervoltage protection turn-off time250µs IOCP Overcurrent protection trip point 3.7 A IOCP OCPOvercurrent protection trip point3.7A tOCP Overcurrent protection deglitch time 2 µs tOCP OCPOvercurrent protection deglitch time2µs tRETRY Retry time 1.7 ms tRETRY RETRYRetry time1.7ms TTSD Thermal shutdown temperature 150 175 °C TTSD TSDThermal shutdown temperature150175°C THYS Thermal shutdown hysteresis 40 °C THYS HYSThermal shutdown hysteresis40°C I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns I2C Timing Requirements MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT STANDARD MODE fSCL SCL Clock frequency 0 100 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU,STA Setup time for a repeated START condition 4.7 µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 1000 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs FAST MODE fSCL SCL Clock frequency 0 400 kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU,STA Setup time for a repeated START condition 0.6 µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tSU,DAT Data set-up time 250 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns tSU,STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns STANDARD MODE STANDARD MODE fSCL SCL Clock frequency 0 100 kHz fSCL SCLSCL Clock frequency0100kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated 4µs tLOW LOW period of the SCL clock 4.7 µs tLOW LOWLOW period of the SCL clock4.7µs tHIGH HIGH period of the SCL clock 4 µs tHIGH HIGHHIGH period of the SCL clock4µs tSU,STA Setup time for a repeated START condition 4.7 µs tSU,STA SU,STASetup time for a repeated START condition4.7µs tHD,DAT Data hold time: For I2C bus devices 0.035 3.45 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0353.45µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 1000 ns tR RSDA and SCL rise time1000ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 4 µs tSU,STO SU,STOSet-up time for STOP condition4µs tBUF Bus free time between a STOP and START condition 4.7 µs tBUF BUFBus free time between a STOP and START condition4.7µs FAST MODE FAST MODE fSCL SCL Clock frequency 0 400 kHz fSCL SCLSCL Clock frequency0400kHz tHD,STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tHD,STA HD,STAHold time (repeated) START condition. After this period, the first clock pulse is generated0.6µs tLOW LOW period of the SCL clock 1.3 µs tLOW LOWLOW period of the SCL clock1.3µs tHIGH HIGH period of the SCL clock 0.6 µs tHIGH HIGHHIGH period of the SCL clock0.6µs tSU,STA Setup time for a repeated START condition 0.6 µs tSU,STA SU,STASetup time for a repeated START condition0.6µs tHD,DAT Data hold time: For I2C bus devices 0.035 0.9 µs tHD,DAT HD,DATData hold time: For I2C bus devices0.0350.9µs tSU,DAT Data set-up time 250 ns tSU,DAT SU,DATData set-up time250ns tR SDA and SCL rise time 300 ns tR RSDA and SCL rise time300ns tF SDA and SCL fall time 300 ns tF FSDA and SCL fall time300ns tSU,STO Set-up time for STOP condition 0.6 µs tSU,STO SU,STOSet-up time for STOP condition0.6µs tBUF Bus free time between a STOP and START condition 1.3 µs tBUF BUFBus free time between a STOP and START condition1.3µs tSP Pulse width of spikes to be supressed by input noise filter  50 ns tSP SPPulse width of spikes to be supressed by input noise filter 50ns Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Timing Diagrams Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram Input-to-Output Timing Diagram Input-to-Output Timing Diagram I2C Timing Diagram I2C Timing Diagram2 Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Typical Operating Characteristics High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) High-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Low-Side MOSFET On Resistance (mΩ) Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Detailed Description Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Overview The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage. The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. The DRV8234 is a high-performance full-bridge motor driver with ripple counting for position detection, motor speed and voltage regulation, stall detection, integrated current sense, and integrated current regulation. The Ripple Counting feature integrates DC motor relative position and speed detection in the device thereby reducing external components on a PCB and saving cost. The principle is based on counting the number of current ripples appearing in the motor current waveform due to commutations. Motor speed regulation feature maintains constant motor speed over varying battery voltages. The voltage regulation feature saves energy by driving the motor with a programmable lower terminal voltage.The DRV8234 uses a standard 2-pin (EN/IN1& PH/IN2) PH/EN-PWM interface and I2C interface for configuration and detailed diagnostics. The EN/IN1 & PH/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 600 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 200 kHz. The PMODE bit in I2C registers allow operating the H-bridge in two different control modes. I2C interface reduces number of GPIO inputs in high motor-count systems and reduces firmware control effort.2DS(ON)22The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The DRV8234 also has I2C programmable registers to configure a hardware stall detection feature based on the IPROPI current sensing signal.2The integrated protection features protect the device in case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. Additionally, the overvoltage protection (OVP) feature puts the driver into the brake state when the motor is spun manually while the device is in sleep mode or when the H-bridge is disabled. This prevents the back EMF induced high voltages on the supply rail that could potentially damage the driver and other circuits in the system.To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and the corresponding capacitors. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity. Functional Block Diagram Functional Block Diagram Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Feature Description External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ External Components #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 lists the recommended external components for the device. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ #GUID-00258417-27E4-4C5C-82B0-B75C767833C5/T5859359-9 Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated. CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated. CVM2 VM GND Bulk Capacitance, VM-rated. CVM2 VM2VMGND Bulk Capacitance, VM-rated.Bulk Capacitance RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level. RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level. Resistor from IPROPI pin to GND, sets the current regulation level. RnFAULT System VCC nFAULT 10 kΩ RnFAULT nFAULTSystem VCC nFAULT nFAULT10 kΩ RRC_OUT System VCC RC_OUT 10 kΩ RRC_OUT RC_OUTSystem VCC RC_OUT RC_OUT10 kΩ RPull-up SDA, SCL, A0, A1 VM 2.2 kΩ RPull-up Pull-upSDA, SCL, A0, A1 VM2.2 kΩ Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH Summary of Features This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH This section includes a summary of the key and advanced features of DRV8234. DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Bridge Control Protection Advanced: Stall Detection Advanced: Ripple Counting Advanced: Error Correction Advanced: Speed and Voltage Regulation Advanced: Soft-Start and Soft-Stop using tINRUSH DRV8234 Functional Block Diagram DRV8234 Functional Block Diagram Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Bridge Control Bridge Control Protection ProtectionAdvanced: Stall Detection Stall DetectionAdvanced: Ripple Counting Ripple CountingAdvanced: Error Correction Error CorrectionAdvanced: Speed and Voltage Regulation Speed and Voltage RegulationAdvanced: Soft-Start and Soft-Stop using tINRUSH Soft-Start and Soft-StoptINRUSH INRUSH Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2. The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths The truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram The tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8234 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two inputs EN/IN1 and PH/IN2 or the I2C bits I2C_EN_IN1 and I2C_PH_IN2.2The I2C_BC bit determines whether the bridge is controlled by the EN/IN1 and PH/IN2 pins or the I2C_EN_IN1 and I2C_PH_IN2 bits, as shown below. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. H-Bridge Control Interface I2C_BC Description 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. I2C_BC Description I2C_BC Description I2C_BCDescription 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 0b Bridge control configured by using the EN/IN1 and PH/IN2 pins. 0bBridge control configured by using the EN/IN1 and PH/IN2 pins. 1b Bridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits. 1bBridge control configured by using the I2C_EN_IN1 and I2C_PH_IN2 bits.The control interface is selected by the PMODE bit, as shown below. PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Functions PMODE Control Mode 0b PH/EN 1b PWM PMODE Control Mode PMODE Control Mode PMODEControl Mode 0b PH/EN 1b PWM 0b PH/EN 0bPH/EN 1b PWM 1bPWMThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. Following diagram shows how the motor current flows through the H-bridge. The input pins can be powered before VM is applied. H-Bridge Current Paths H-Bridge Current Paths H-Bridge Current PathsThe truth tables for each control mode are shown below. Note that these tables do not take into account the internal current regulation feature. Additionally, when an output changes from driving high to driving low (or driving low to driving high), dead time is automatically inserted to prevent shoot-through.PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown below. PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay PH/EN Control Mode (PMODE = 0b) nSLEEP Enable Phase OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP Enable Phase OUT1 OUT2 Description nSLEEP nSLEEPEnablePhaseOUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 1 0 L H Reverse (Current OUT2 → OUT1) 1 11 0 0LHReverse (Current OUT2 → OUT1) 1 1 1 H L Forward (Current OUT1 → OUT2) 1 111HLForward (Current OUT1 → OUT2) 1 0 X L L Brake; low-side slow decay 1 10XLLBrake; low-side slow decay Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Enable refers to the EN pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Phase refers to the PH pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). PWM mode allows for the H-bridge to enter the High-Z state while the device is awake. The truth table for PWM mode is shown below. PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay PWM Control Mode (PMODE = 1b) nSLEEP Input1 Input2 OUT1 OUT2 Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP Input1 Input2 OUT1 OUT2 Description nSLEEP nSLEEPInput1Input2OUT1OUT2Description 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 0 X X High-Z High-Z Sleep Mode (H-bridge High-Z) 0 0XXHigh-ZHigh-ZSleep Mode (H-bridge High-Z) 1 0 0 High-Z High-Z Coast (H-bridge High-Z) 1 10 0 0High-ZHigh-ZCoast (H-bridge High-Z) 1 0 1 L H Reverse (Current OUT2 → OUT1) 1 101LHReverse (Current OUT2 → OUT1) 1 1 0 H L Forward (Current OUT1 → OUT2) 1 1 1 10HLForward (Current OUT1 → OUT2) 1 1 1 L L Brake; low-side slow decay 1 1 1 1 1 1 L L L LBrake; low-side slow decay Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). Input1 refers to the IN1 pin when bridge control is external (I2C_BC=0b), and the I2C_EN_IN1 bit when bridge control is internal (I2C_BC=1b). Input2 refers to the IN2 pin when bridge control is external (I2C_BC=0b), and the I2C_PH_IN2 bit when bridge control is internal (I2C_BC=1b). The following timing diagram shows the timing of the inputs and outputs of the motor driver. H-Bridge Timing Diagram H-Bridge Timing DiagramThe tDEAD time is the time in the middle when the output is High-Z. The output pin voltage during tDEAD depends on the direction of the output current. If the current is sourced from the pin, the voltage is a diode voltage drop below ground. If the current is sunk to pin, the voltage is a diode voltage drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Sense and Regulation (IPROPI) The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8234 integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in case of motor stall or high load torque events. The IPROPI output provides a current output proportional to the load current. This IIPROPI current can be converted to a VIPROPI output voltage by connecting a suitable resistor RIPROPI from this pin to the circuit ground. The following diagram shows the IPROPI timings specified in the Electrical Characteristics table.IPROPIIPROPIIPROPI Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A. The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated as shown below - VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by the following equation. The ILSx in the equation is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. It indicates the combined effect of offset error added to the IOUT current and gain error. The current mirror gain AIPROPI is fixed at 1500 μA/A.ERRIPROPIOUTIPROPIThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown below. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin should be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8234 implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This ensures good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI will have good accuracy up to 2.05 V.IPROPIIPROPIIPROPIIPROPIIPROPIIPROPIVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated as shown below -VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the truth tables), the IPROPI output will disable with the input logic signal. Although the low-side MOSFETs may still conduct current as they disable according to the device slew rate (specified in the Electrical Characteristics table by tRISE time), IPROPI will not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Current Regulation The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C. The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table. REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V. The ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit. The IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times The DRV8234 integrates current regulation using either a fixed off-time or a cycle-by-cycle PWM current regulation scheme. This allows the device to limit the output current in case of a motor stall, high torque, or other high current load events autonomously. The current regulation scheme is selectable by the REG_CTRL bit in I2C.2The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND if current feedback is not required. Additionally, current regulation can also be disabled by setting IMODE to 00b as explained below. If current feedback is required and current regulation is not required, set VVREF and RIPROPI such that VIPROPI never reaches the VVREF threshold. For proper operation of the current regulation circuit, VVREF must be within the range of the VREF pin voltage specified in the Recommended Operating Conditions table.VREFIPROPIIPROPIVREFVREF REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle REG_CTRL Functions Bit* Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle Bit* Current Regulation Mode Bit* Current Regulation Mode Bit*Current Regulation Mode 00b Fixed Off-Time 01b Cycle-By-Cycle 00b Fixed Off-Time 00bFixed Off-Time 01b Cycle-By-Cycle 01bCycle-By-Cycle *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in . *Additional REG_CTRL options 10b and 11b allow selection between motor voltage or speed regulation described in .The current regulation threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 1100 Ω and AIPROPI = 1500 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. If INT_VREF bit is set to 1b, VVREF is internally selected with a fixed value of 3 V.VREFVMVREFVREFThe ITRIP comparator has both a blanking time (tBLANK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from affecting the current regulation. These transients may be caused by a capacitor inside the motor or motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, helps filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be modified as needed, however large capacitor values may slow down the response time of the current regulation circuit.TRIPBLANKDEGThe IMODE bits determine the behavior of current regulation for the motor driver. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 10b, current regulation is enabled at all times. When IMODE is 00b, current regulation is disabled. When IMODE is 00b, current regulation is disabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled. When IMODE is 01b, the device performs current regulation only during the tINRUSH time when stall detection is enabled.INRUSH When IMODE is 10b, current regulation is enabled at all times. When IMODE is 10b, current regulation is enabled at all times.The following table summarizes the IMODE bit settings. IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE configuration IMODE EN_STALL Description 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times IMODE EN_STALL Description IMODE EN_STALL Description IMODE EN_STALL EN_STALLDescription 00b X No current regulation at any time 01b 0b Current regulation at all times 1b Current regulation during tINRUSH only 1Xb X Current regulation at all times 00b X No current regulation at any time 00b 00bXNo current regulation at any time 01b 0b Current regulation at all times 01b 0b 0bCurrent regulation at all times 1b Current regulation during tINRUSH only 1b 1bCurrent regulation during tINRUSH onlyINRUSH 1Xb X Current regulation at all times 1Xb 1XbXCurrent regulation at all times Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs. Fixed Off-Time Current Regulation Fixed Off-Time Current RegulationIn the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs or I2C_EN_IN1 or I2C_PH_IN2 bits changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFOUTTRIPOFFOUTTRIPOUTTRIPOFFOFFOFFThe fixed off-time mode allows for a simple current regulation scheme independent of the external controller. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the control input pins or bits to reset the outputs.OFF Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered. Cycle-By-Cycle Current Regulation In cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset. Cycle-By-Cycle Current Regulation, CBC_REP = 1b No device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on either the EN/IN1 or PH/IN2 pins or 0 to 1 transitions on the I2C_EN_IN1 or I2C_PH_IN2 bits. This allows for additional control of the current regulation by the external controller. This is shown in the diagram below. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.OUTTRIP Cycle-By-Cycle Current Regulation Cycle-By-Cycle Current RegulationIn cycle-by-cycle mode, the device can indicate whenever the H-bridge enters internal current regulation by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This behavior is controlled by the CBC_REP bit. This is shown in the following diagram. In cycle-by-cycle mode, if the CBC_REP bit is 1b, nFAULT will be pulled low when the H-bridge enters internal current regulation and nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.TRIP Cycle-By-Cycle Current Regulation, CBC_REP = 1b Cycle-By-Cycle Current Regulation, CBC_REP = 1bNo device functionality is affected when the nFAULT pin is pulled low for the current regulation indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault from the current regulation indicator, the nFAULT pin can be compared with the control inputs. The current regulation indicator can only assert when the control inputs are commanding a forward or reverse drive state. If the nFAULT pin is pulled low and the control inputs are commanding the high-Z or slow-decay states, then a device fault has occurred. Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response. Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V The STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier. The TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF. When voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time. When voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB The SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. The IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see . The STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output. The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation The DRV8234 integrates a stall detection feature. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin or 3 V to determine whether a motor stall condition has occurred. The setting is deterimed by the INT_VREF register. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0 shows the configurable options for INT_VREF. The following paragraphs describe how to configure the I2C registers for the desired stall detection response.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF02 Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Settings for INT_VREF Bit Description 0b VVREF not fixed 1b VVREF fixed internally at 3 V Bit Description Bit Description BitDescription 0b VVREF not fixed 1b VVREF fixed internally at 3 V 0b VVREF not fixed 0bVVREF not fixedVREF 1b VVREF fixed internally at 3 V 1bVVREF fixed internally at 3 VVREFThe STALL bit in status register changes to 1b when a motor stall is detected. The EN_STALL bit is used to enable or disable stall detection. The following table summarizes the EN_STALL bit settings. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL configuration EN_STALL Description 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. EN_STALL Description EN_STALL Description EN_STALLDescription 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 1b Stall detection enabled. 0b Stall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF. 0bStall detection disabled. If IMODE = 01b, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF 1b Stall detection enabled. 1bStall detection enabled.The IPROPI pin provides the current sense signal to the stall detection module. The VREF pin sets the ITRIP current level at which a stall condition is detected. As shown in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0, VVREF is internally fixed at 3 V when INT_VREF = 1b. When VIPROPI ≥ VVREF, it implies IOUT ≥ ITRIP. The device detects a stall condition here. Stall detection is blanked for a period of time, tINRUSH, to avoid false detection due to high inrush currents during motor startup. The IPROPI and VREF pins also support current regulation, as described earlier.TRIP#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/GUID-96B0E913-D686-438C-A54A-34C67FF73DF0VREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH[15:0] bits set the period of time the stall detection logic will ignore the inrush current during motor startup (tINRUSH). After tINRUSH time expires, the DRV8234 indicates a stall condition the next instant VIPROPI is greater than or equal to VVREF.INRUSHINRUSHIPROPIVREFWhen voltage or speed soft-start is disabled, the tINRUSH time directly reflects the setting of the TINRUSH bits. The tINRUSH can be set to a value between 5 ms (corresponding to 0000h) and 6.7 s (corresponding to FFFFh), with a default value of 1 s. Each increment of LSB corresponds to 102.4 μs of the inrush time.INRUSHINRUSHWhen voltage or speed soft-start is enabled, target motor voltage or speed is soft-started and soft-stopped for the duration of tINRUSH time. The TINRUSH bits should be setup such that the tINRUSH = TINRUSH bit setting x WSET_VSET. For example, if WSET_VSET = 10 and intended inrush time is 1 s, then TINRUSH bit setting should correspond to 100 ms.INRUSHINRUSHThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8234 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB Power-up of the DRV8234 Power-up of the DRV8234 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTBThe SMODE bit programs the device's response to a stall condition. When SMODE = 0b, the outputs disable, and the STALL bit becomes 1b. When SMODE = 1b, the STALL bit becomes 1b, but the outputs continue to drive current into the motor. #GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB summarizes the SMODE bit settings.#GUID-E87E3829-E22C-414A-9E96-2E0762B34B98/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE configuration SMODE Description Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0b Latched disable with indication: the OUTx pins disable and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 0bLatched disable with indication: the OUTx pins disable and the STALL bit becomes 1b.A clear fault must be issued by writing 1b to the CLR_FLT bit. STALL bit changes to 0b after a clear fault is issued. After waking up from stall, the stall detection scheme ignores the inrush current for tINRUSH time as described earlier. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHINRUSHTRIP 1b Indication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. 1b 1bIndication only: the OUTx pins remain active and the STALL bit becomes 1b. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again. A clear fault must be issued by writing 1b to the CLR_FLT bit to make STALL bit 0b. After tINRUSH time, if motor current is still higher than ITRIP, a stall condition is detected again.INRUSHTRIPThe IMODE bits determine the behavior of current regulation in the motor driver. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEThe STALL_REP bit determines whether stall is reported on nFAULT pin. When STALL_REP bit is 1b, nFAULT is pulled low whenever stall is detected and STALL bit is 1b. If STALL_REP bit is 0b, stall is not reported on nFAULT output.The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with STALL indication only Stall Detection with STALL indication only Stall Detection with current regulation during inrush Stall Detection with current regulation during inrush Stall Detection with current regulation Stall Detection with current regulation Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors. The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity. Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve. To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram In applications such as electronic locks and gas valves, it may be required to identify the rotor position or speed of the brushed-DC motor to implement a variety of different functions at the system level. Most systems implement position or speed detection using encoders, limit switches or Hall sensors.The DRV8234 supports an integrated Ripple counting algorithm to estimate motor position and speed without using any external sensors such as an encoder or a Hall sensor. This enables reduction in system BOM count, BOM cost, and design complexity.Ripple counting with integrated stall detection allows increased system reliability. For example, in a gas valve system, although the timing of stall detection may change due to changes in temperature and gas pressure, the number of ripples before stall will be same for each actuation. If a stall occurs, but the number of ripples is less than the target value, then this may indicate a loss of position, for example due to a jammed valve.To enable the ripple counting feature, set EN_RC to 1b. Ripple couting block diagram Ripple couting block diagram Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Ripple Counting Parameters To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. To achieve an accurate ripple count, the following parameters must be configured accurately. Refer to for additional details. Refer to for the detailed tuning procedure. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Denoted by INV_R, this is the equivalent of the conductance (inverse of resistance) of the motor scaled by a scaling factor, INV_R_SCALE. Scaling allows a wide range of motor resistance values to be accepted using the combination of INV_R and INV_R_SCALE. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Motor Resistance Inverse Scale Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF. Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E Please note that the maximum value of INV_R is 255. Denoted by INV_R_SCALE, this is the scaling factor for the inverse of motor resistance (INV_R). Since the inverse of a motor resistance is generally not an integer, the value must be rounded off to the nearest integer. Settings are described in #GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF.#GUID-F7E6B802-6CFA-4B28-8964-3F478CD48ABF Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Settings for INV_R_SCALE Bit Value of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 Bit Value of INV_R_SCALE Bit Value of INV_R_SCALE BitValue of INV_R_SCALE 00b 2 01b 64 10b 1024 11b 8192 00b 2 00b2 01b 64 01b64 10b 1024 10b1024 11b 8192 11b8192INV_R is represented by the equation: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEPlease note that the maximum value of INV_R is 255. KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 KMC Scaling Factor Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E Where, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: N R = L C M N B , N C Please note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Denoted by KMC_SCALE, this is a scaling factor for the parameter KMC. KMC is represented by the following equation: K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E K M C =   K V N R × K M C _ S C A L E KMC=  K V N R K V K V K K V V N R N R N N R R×KMC_SCALEWhere, KV is the motor back emf constant and NR is the number of ripples per revolution. NR is calculated by taking the LCM (Least Common Multiple) of the number of brushes, NB, and the number of commutators, NC: VRRBC N R = L C M N B , N C N R = L C M N B , N C N R = L C M N B , N C N R N N R R=LCM N B , N C N B , N C N B N N B B, N C N N C CPlease note that LCM can be easily calculated by using any online LCM calculator. Tuning KMC appropriately is critical for the ripple counting algorithm to perform accurately. Scaling is done because the value of motor back emf constant is generally small. Scaling allows integer values to be written on to registers. Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Settings for KMC_SCALE Bit Value of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 Bit Value of KMC_SCALE Bit Value of KMC_SCALE BitValue of KMC_SCALE 00b 24 x 28 01b 24 x 29 10b 24 x 212 11b 24 x 213 00b 24 x 28 00b24 x 28 8 01b 24 x 29 01b24 x 29 9 10b 24 x 212 10b24 x 212 12 11b 24 x 213 11b24 x 213 13 KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. KMC This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure. This register is a motor constant representing a proportional value of the motor back emf constant. See KMC Tuning for a detailed tuning procedure.KMC Tuning Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Damping Constant Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the ripples in the motor current waveform. Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Filter Input Scaling Factor Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Settings are mentioned below. Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Settings for FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 Bit Value of FLT_GAIN_SEL Bit Value of FLT_GAIN_SEL BitValue of FLT_GAIN_SEL 00b 2 01b 4 10b 8 11b 16 00b 2 00b2 01b 4 01b4 10b 8 10b8 11b 16 11b16 Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Ripple Count Threshold Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation. Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation: N R T = R C _ T H R × R C _ T H R _ S C A L E The parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. Denoted by RC_THR, this parameter represents the threshold setting for the total number of ripple counts vs the total number of ripple counts estimated by the ripple counting algorithm based on the expected time of motor actuation.Let NRT be the number of ripples at threshold. Then, RC_THR is represented by the equation:RT N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T = R C _ T H R × R C _ T H R _ S C A L E N R T N N R T RT=RC_THR×RC_THR_SCALEThe parameters further involved in ripple counting threshold are as follows: RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT. RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT. CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b. RC_CNT is a 16-bit register which corresponds to the number of current ripples counted. When RC_CNT exceeds NRT, CNT_DONE is latched high. RC_CNTRT CNT_DONE is a status register that latches high when RC_CNT exceeds NRT. This register can be cleared by using CLR_CNT.CNT_DONERT RC_REP decides if nFAULT maintains previous value or is pulled low when RC_CNT exceeds NRT.RC_REPRT CLR_CNT, when set to 1b, resets NRT to 0 and CNT_DONE to 0b.CLR_CNTRT Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Ripple Count Threshold Scale Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Denoted by RC_THR_SCALE, this is the scaling factor for the number of ripples for threshold. Settings are given below. Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Settings for RC_THR_SCALE Bit Value of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 Bit Value of RC_THR_SCALE Bit Value of RC_THR_SCALE BitValue of RC_THR_SCALE 00b 2 01b 8 10b 16 11b 64 00b 2 00b2 01b 8 01b8 10b 16 10b16 11b 64 11b64Depending on the number of ripples per revolution, NR, and the speed of rotations, RC_THR_SCALE can be chosen high or low based on user requirement of the nFAULT pin. If total number of ripple counts until the end of an operation cycle are low, choose a lower value of RC_THR_SCALE, otherwise a higher value is recommended.R Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. Please note that RC_THR and RC_THR_SCALE do not affect the accuracy of ripple counting. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter filters out the noise based on the voltage difference between the output pins. The digital filter multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3. When analog filter is selected, the cut-off frequency can be selected by the OUT_FLT register. #GUID-D48B7D29-F349-4148-82F9-D592B649FE2A/GUID-CC3EBDE4-0CA8-4C0A-9AB6-E60AFD66F3A3OUT_FLT Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Settings for VSNS_SEL Bit Description 0b Analog Output Filter 1b Digital Output Filter Bit Description Bit Description BitDescription 0b Analog Output Filter 1b Digital Output Filter 0b Analog Output Filter 0bAnalog Output Filter 1b Digital Output Filter 1bDigital Output Filter Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. Error Correction Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS. DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Error correction involves the use of two registers, DIS_EC and EC_PULSE_DIS.DIS_EC is used to enable/disable the error correction block shown in . shows the settings for DIS_EC. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Settings for DIS_EC Bit Description 0b Error Correction block is enabled. 1b Error Correction block is disabled. Bit Description Bit Description BitDescription 0b Error Correction block is enabled. 1b Error Correction block is disabled. 0b Error Correction block is enabled. 0bError Correction block is enabled. 1b Error Correction block is disabled. 1bError Correction block is disabled.EC_PULSE_DIS is used to enable/disable the output of the Error Correction block when the Error Correction block is enabled. describes the settings of EC_PULSE_DIS in detail. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Settings for EC_PULSE_DIS Bit Status of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Bit Status of Error Correction block output Bit Status of Error Correction block output BitStatus of Error Correction block output 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. 0b Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Please note that the Error Correction block is active in this setting. Output follows settings for DIS_EC as displayed in . If DIS_EC is set to 0b, RC_OUT continues to output pulses even when the motor is: Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected, Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. Disconnected,Connected but not rotating, or Stalled (depending on the settings for SMODE), if ripple counting is enabled. SMODEPlease note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. 1b Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Please note that the Error Correction block is active in this setting. Output is disabled if the following two conditions are met: Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, and The bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses. Error corrector adds 12 consecutive pulses, andThe bandpass filter does not give any pulse output during the time period of the 12 consecutive pulses.Please note that the Error Correction block is active in this setting. summarizes the settings described above. Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses Summary of Error Correction DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_EC EC_PULSE_DIS Error Corrector Status Output Pulse Status DIS_ECEC_PULSE_DISError Corrector StatusOutput Pulse Status 0b 0b Enabled Pulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 0b 0b Enabled Pulse train output from RC_OUT 0b0bEnabledPulse train output from RC_OUT 0b 1b Enabled No pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 0b1bEnabledNo pulses only if Error Corrector adds 12 consecutive pulses and bandpass filter gives no output. 1b X Disabled No Pulses 1bXDisabledNo Pulses EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. EC_FALSE_PER is a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples.EC_FALSE_PERafter EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PER is a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector takes action if an expected current ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. EC_MISS_PERexpected RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. RC_OUT Output The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. The RC_OUT pin has an open-drain output and is to be pulled up to a 5-V or 3.3-V supply. The RC_OUT pin outputs a pulse train corresponding to the number of ripples in the motor current. The positive pulse width of the pulse train is 50 μs. Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting with nFAULT The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b The DRV8234 allows the nFAULT pin to be configured for various settings of RC_CNT using the RC_REP register. lists the settings for the RC_REP register (refer to for details). Timing diagrams corresponding to RC_REP settings are shown in and . RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP Settings RC_REP nFAULT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. RC_REP nFAULT RC_CNT RC_REP nFAULT RC_CNT RC_REP RC_REP RC_REP nFAULT nFAULT nFAULT RC_CNT RC_CNT RC_CNT 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 00b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 00b 00b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 01b Ripple counting has no effect on nFAULT If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 01b 01b Ripple counting has no effect on nFAULT Ripple counting has no effect on nFAULTIf RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 10b nFAULT is pulled low if RC_CNT exceeds threshold If RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued. 10b 10b nFAULT is pulled low if RC_CNT exceeds threshold nFAULT is pulled low if RC_CNT exceeds thresholdIf RC_CNT reaches the maximum value of 216 - 1, it is held at that value until a CLR_CNT command is issued.16 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0. 11b 11b nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 1 nFAULT is pulled low for 50 μs if RC_CNT reaches the maximum value of 216 - 116If RC_CNT reaches the maximum value of 216 - 1, RC_CNT is cleared and restarted from 0.16 Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 11b Ripple Counting Timing with RC_REP = 10b Ripple Counting Timing with RC_REP = 10b Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Motor Voltage and Speed Regulation The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life. The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation. Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control The DRV8234 provides the ability to regulate the voltage applied to the motor winding or to regulate the speed of the motor. This feature allows constant motor speed to be maintained even when operating from a varying supply voltage such as a discharging battery. The DRV8234 uses a pulse-width modulation (PWM) technique instead of a linear circuit to minimize current consumption and maximize battery life.The intended voltage or speed can be programmed by the WSET_VSET bits. Refer to for further explanation.Four ranges of motor speed can be selected using the W_SCALE bits to support low, moderate and high speed applications. The speed regulation loop compares the motor speed estimated by the ripple counting algorithm with the user definded target speed. The following section describes the internal bridge control logic taking voltage regulation as an example, but is also applicable for speed regulation. shows the closed loop PI control for regulating speed and voltage. Speed and Voltage Regulation with PI Control Speed and Voltage Regulation with PI Control Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Internal Bridge Control For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. The DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode. When Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. For voltage regulation, an internal circuit monitors the voltage difference between the output pins. This voltage difference is integrated over time to get an average DC voltage value. The time depends on the cut-off frequency of the output filter which can be set by the OUT_FLT register. For best results, choose a cut-off frequency setting equal to at least ten times the PWM frequency. OUT_FLTThe DC voltage value is compared to the target motor voltage programmed by the I2C register, WSET_VSET. During voltage as well as speed regulation modes, an internal bridge control scheme is employed. PMODE is used to select the PH/EN mode or the PWM mode.2WSET_VSETWhen Voltage or Speed Regulation mode is active, DUTY_CTRL must be set to 0b. Bridge control is internal in this case. Duty cycle can be programmed by using the IN_DUTY register.DUTY_CTRLIN_DUTY If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is lower than VSET, the duty cycle of the internal bridge control output is increased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. If the averaged output voltage is higher than VSET, the duty cycle of the internal bridge control output is decreased. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on time. The current flow direction depends on the EN/IN1 and PH/IN2 polarity. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. During the PWM off time, winding current is recirculated by enabling both of the low-side FETs in the bridge. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. If the programmed output voltage (VSET) is greater than the VM supply voltage, the device operates at 100% duty cycle and the voltage regulation feature is disabled. In this mode, the device behaves like a conventional H-bridge driver. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. Setting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. The IN_DUTY register outputs the actual duty cycle of the internal bridge control scheme in voltage regulation mode. PWM_FREQ sets the PWM frequency for internal PWM generation. IN_DUTYPWM_FREQSetting DUTY_CTRL to 1b enables the user to program the duty cycle into EXT_DUTY for external bridge control. For using the internal bridge control scheme, DUTY_CTRL must be set to 0b. IN_DUTY can then be used to program the desired duty cycle. PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz PWM_FREQ Settings Bit Value 0b 25 kHz 1b 50 kHz Bit Value Bit Value BitValue 0b 25 kHz 1b 50 kHz 0b 25 kHz 0b25 kHz 1b 50 kHz 1b50 kHz In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. In voltage regulation mode, the motor speed can vary slightly because the voltage drop across the motor coil resistance introduces a small error. The speed regulation mode eliminates this error by directly regulating the target motor speed. To enable speed regulation, the REG_CTRL bit must be set to 10b. Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Setting Speed/Voltage Regulation Parameters For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). For obtaining an accurate output from speed and voltage regulation, the following parameters need to be set (for an in-depth explanation, refer to ). Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Speed and Voltage Set Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting. When REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that: T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E When REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V. For example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. Denoted by WSET_VSET, this parameter helps set the target ripple speed or motor voltage, based on the REG_CTRL register setting.REG_CTRLWhen REG_CTRL is set to 10b, the speed regulation mode is enabled. WSET_VSET is an 8-bit register and can be set to a value between 00h (corresponds to 0 rad/s) and FFh (corresponds to the maximum speed allowable by W_SCALE). The speed control loop matches the value of the SPEED register to the target speed set by WSET_VSET. Please note that the maximum value of the SPEED register is 255. Also note that:REG_CTRLW_SCALEspeed control loopSPEEDSPEED T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E T a r g e t   R i p p l e   S p e e d = S P E E D   × W _ S C A L E Target Ripple Speed=SPEED ×W_SCALEWhen REG_CTRL is set to 11b, the motor voltage regulation mode is enabled. The motor voltage in this case can be set to a value between 0 for 0 V and 255 for approximately 42.67 V drive output voltage. Please note that the maximum value of WSET_VSET is 255. Each bit corresponds to approximately a 0.167 mV resolution of the output voltage setting. Setting WSET_VSET to 255 sets the target voltage to approximately 42.7 V.REG_CTRLFor example, if desired target voltage is 5 V, Register Setting Value = 5*(255/42.67) = 29.88. Hence, setting a value of 30 (or 1Eh) outputs approximately 5 V. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. To set the target voltage to 38 V, set WSET_VSET to 227. In practice, the driver's Over Voltage Protection shuts the device down before 42.67 V. The maximum voltage for VM under is 38 V. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy. Recommended to set the target voltage below 38 V for better accuracy.To set the target voltage to 38 V, set WSET_VSET to 227. Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Speed Scaling Factor Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Example setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Denoted by W_SCALE, this is a scaling factor which helps in setting the target ripple speed when speed regulation mode is enabled. Settings for W_SCALE are shown below. This register also sets the maximum value of ripple speed under each setting of W_SCALE. Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Settings for W_SCALE Bit W_SCALE Maximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s Bit W_SCALE Maximum Ripple Speed Bit W_SCALE Maximum Ripple Speed BitW_SCALEMaximum Ripple Speed 00b 16 4080 rad/s 01b 32 8160 rad/s 10b 64 16320 rad/s 11b 128 32640 rad/s 00b 16 4080 rad/s 00b164080 rad/s 01b 32 8160 rad/s 01b328160 rad/s 10b 64 16320 rad/s 10b6416320 rad/s 11b 128 32640 rad/s 11b12832640 rad/sExample setting for W_SCALE: If SPEED register = 15, W_SCALE = 01b, then the actual ripple speed = 15*32=480 rad/s. SPEED Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b). Explanation for Maximum Ripple Speed: W_SCALE inadvertently sets the upper limit for the target ripple speed under that setting of W_SCALE. For example, if W_SCALE = 00b, then the maximum ripple speed under this setting = 255*16 rad/s = 4080 rad/s. Hence, the maximum target speed achievable under this setting is 4080 rad/s. Furthermore, under this setting of W_SCALE, FFh corresponds to 4080 rad/s for WSET_VSET when speed regulation mode is activated (REG_CTRL=10b).REG_CTRL Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. Soft-Start and Soft-Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance. Soft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. Soft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. Soft Start and Soft Stop The DRV8234 integrates a soft-start and stop feature to safeguard the device from high inrush currents during start up. This feature can be activated by setting the EN_SS bit to 1b when the REG_CTRL register is set to 10b (Speed Regulation) or 11b (Voltage Regulation). If speed or voltage regulation modes are inactive, the EN_SS bit has no influence on the device performance.REG_CTRLSoft-start comes into effect during motor start up. The motor current is slowly ramped up to the current value corresponding to the target speed over the duration of tINRUSH time. The inrush time tINRUSH can be set by the user via the 16-bit TINRUSH register. During this time tINRUSH, the FETs are internally PWMed with a duty cycle generated using the PI control loop. INRUSHINRUSHTINRUSH INRUSHSoft-stop results in a slow ramp down of motor current in time tINRUSH. This can be triggered by the following methods: The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. INRUSH The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00. The direction of rotation is changed on-the-fly. The soft stop function prevents a high current build-up through the motor windings by ramping down the current slowly and performing soft-start on the other direction. Setting I2C_EN_IN1 and I2C_PH_IN2 to 0. Please note that this method sets outputs to Hi-Z after triggering soft stop, which deviates from conventional device operation where setting inputs to 0 causes the device to immediately go Hi-Z and enter coast mode. Set WSET_VSET to 0x00.A reference block diagram containing the PI loop can be found in . shows the motor current slow ramp up at start up and ramp down at motor stop within time tINRUSH. block diagramINRUSH Soft Start and Soft Stop Soft Start and Soft Stop TINRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. TINRUSH INRUSH The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. The inrush time, tINRUSH, is set using the 16-bit TINRUSH register. As described earlier, tINRUSH has a dual purpose: tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHTINRUSHINRUSH tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section. Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. tINRUSH is duration of time for which the stall detection scheme ignores the motor inrush current. This prevents false detection of stall during start up. Stall detection is blanked for this duration of time. A detailed description can be found in the Stall Detection section.INRUSHStall Detection Additionally, tINRUSH is also the duration of time for which the soft-start and stop feature ramps up the speed or voltage from 0 to a value set by WSET_VSET, or ramps down the speed or voltage from the existing value to 0. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. INRUSHWSET_VSET When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s. When EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms. When EN_SS is set to 0b, the TINRUSH register bit settings directly reflect the tINRUSH time. Time tINRUSH can be set to a value between 5 ms (0000h) and 6.7 s (FFFFh). Default value is 1 s.TINRUSHINRUSHINRUSHWhen EN_SS is set to 1b during motor speed or voltage regulation mode, the target motor speed or voltage is soft-started and stopped over the duration of tINRUSH as describe above. In this case, tINRUSH = TINRUSH x WSET_VSET. As an example, if WSET_VSET = 10 and intended tINRUSH time is 1 s, then TINRUSH is to be set to 100 ms.INRUSHINRUSHTINRUSHINRUSHTINRUSH Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin Protection Circuits The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. The DRV8234 is fully protected against supply undervoltage, overcurrent, and overtemperature events. In addition, the device supports overvoltage protection in sleep mode and when the H-bridge is disabled. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low. The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event. In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram - OCP Operation In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply. Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.OCPThe OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -RETRYRETRY OCP Operation OCP Operation OCP OperationIn latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature. In automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued. In latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled, TSD and FAULT bits become 1b, and nFAULT is pulled low. The TSD_MODE bit programs the response of the device to overtemperature event. The device can either latch-off or perform automatic retry to recover from overtemperature.TSDIn automatic retry mode, normal operation will resume (driver operation starts, nFAULT is released and FAULT bit changes to 0b) when the junction temperature falls below the overtemperature threshold limit minus the hysteresis (TTSD – THYS). The TSD bit remains at 1b indicating that a thermal shutdown event occurred until a CLR_FLT command is issued.TSDHYSIn latch-off mode, once the overtemperature condition is removed, normal operation resumes after sending a CLR_FLT command, or a power cycling. VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile VM Undervoltage Lockout (VM UVLO) If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage: All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low Normal operation resumes when the VM voltage recovers above the UVLO rising threshold. If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST: I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low From this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile When the voltage on the VM pin falls below the VRST: I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high During a subsequent power-up, when the VM voltage exceeds the VRST voltage: The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. Supply Voltage Ramp Profile All the outputs are disabled (High-Z) The internal charge pump is disabled nFAULT is driven low All the outputs are disabled (High-Z) All the outputs are disabled (High-Z) The internal charge pump is disabled The internal charge pump is disabled nFAULT is driven low nFAULT is driven lowNormal operation resumes when the VM voltage recovers above the UVLO rising threshold.If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:RST I2C communication is available and the digital core of the device is active The FAULT and UVLO bits are made high The nFAULT pin is driven low I2C communication is available and the digital core of the device is active I2C communication is available and the digital core of the device is active2 The FAULT and UVLO bits are made high The FAULT and UVLO bits are made high The nFAULT pin is driven low The nFAULT pin is driven lowFrom this condition, if the VM voltage recovers above the UVLO rising threshold voltage: nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. nFAULT pin is released (is pulled-up to the external voltage) nFAULT pin is released (is pulled-up to the external voltage) The FAULT bit is reset The FAULT bit is reset The UVLO bit remains latched high until cleared through the CLR_FLT command. The UVLO bit remains latched high until cleared through the CLR_FLT command. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Supply Voltage Ramp ProfileRST I2C communication is unavailable and the digital core is shutdown The FAULT and UVLO bits are low The nFAULT pin is high I2C communication is unavailable and the digital core is shutdown I2C communication is unavailable and the digital core is shutdown2 The FAULT and UVLO bits are low The FAULT and UVLO bits are low The nFAULT pin is high The nFAULT pin is highRST The digital core comes alive UVLO bit stays low The FAULT bit is made high The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. The digital core comes alive The digital core comes alive UVLO bit stays low UVLO bit stays low The FAULT bit is made high The FAULT bit is made high The nFAULT pin is pulled low The nFAULT pin is pulled low When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. When the VM voltage exceeds the VM UVLO rising threshold FAULT bit is reset UVLO bit stays low nFAULT pin is pulled high. FAULT bit is reset FAULT bit is reset UVLO bit stays low UVLO bit stays low nFAULT pin is pulled high. nFAULT pin is pulled high. Supply Voltage Ramp Profile Supply Voltage Ramp Profile Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. Overvoltage Protection (OVP) When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals. The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset. In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. When the motor is driven by external force, it acts as a generator and pumps back current to the supply voltage rail. This can potentially damage other circuits connected to the supply rail. In low-power sleep mode or when the H-bridge is disabled (High-Z), if the voltage of the output nodes rise above the supply voltage by about 200 mV, the DRV8234 turns on the two low-side MOSFETs. This allows the device to actively brake a motor connected to the outputs by shorting the back emf across the motor terminals.The overvoltage protection (OVP) function is enabled by default. After power-up, the EN_OVP bit can be made 0b to disable this feature. The EN_OVP logic state is latched, so that in sleep mode the device bahves as per the EN_OVP bit setting, even though the internal digital logic is reset.In sleep mode, if there is a short circuit to power supply fault present in the power stage, a simple overcurrent detector circuit is provided to disable the low-side MOSFET if a high current event is detected while braking. This is needed since the normal overcurrent protection circuits are disabled during the low-power sleep mode. nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Output The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin The nFAULT pin has an open-drain output and should be pulled up to a 5-V or 3.3-V supply. nFAULT pin will be high after power-up. When a fault is detected, the nFAULT pin will be logic low. nFAULT Pin nFAULT Pin Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Device Functional Modes The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section The following table summarizes the DRV8234 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Fault Mode Any fault condition met Disabled See Fault Mode section Active Mode nSLEEP = 1, EN_OUT = 1b Operating Operating Active ModenSLEEP = 1, EN_OUT = 1b = 1, EN_OUT = 1bOperatingOperating Low-Power Sleep Mode nSLEEP = 0 Disabled Disabled Low-Power Sleep ModenSLEEP = 0 = 0DisabledDisabled Fault Mode Any fault condition met Disabled See Fault Mode section Fault ModeAny fault condition metDisabledSee Fault Mode section Fault Mode section Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. Active Mode After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs. After the supply voltage on the VM pin has crossed the rising undervoltage threshold, if nSLEEP is logic high and tWAKE has elapsed, and if the EN_OUT bit is 1b, the device enters active mode. In this mode, the full-bridge, and internal logic are active and the device is ready to receive inputs.WAKE Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. Low-Power Sleep Mode When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational. When the nSLEEP pin is low for tTURNOFF time, the DRV8234 enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin. After nSLEEP is set high for longer than the duration of tWAKE, the device becomes fully operational.TURNOFFSLEEPWAKE Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Mode The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD The DRV8234 enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.#GUID-21A5B48C-F5AA-43D2-9DD6-65C785FC4019/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Fault Conditions Summary FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION CONFIGURATION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION CONFIGURATION CONFIGURATION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD VM undervoltage (VM UVLO) VVM < VUVLO_VM _ nFAULT / I2C Disabled Disabled VVM > VUVLO_VM VM undervoltage (VM UVLO) VM undervoltage (VM UVLO) VVM < VUVLO_VM VVM < VUVLO_VM VMUVLO_VM_nFAULT / I2C2DisabledDisabledVVM > VUVLO_VM VMUVLO_VM Overcurrent (OCP) IOUT > IOCP OCP_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Overcurrent (OCP)IOUT > IOCP OUTOCP OCP_MODE = 0b OCP_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperating Latched: CLR_FLT Latched: CLR_FLT OCP_MODE = 1b nFAULT / I2C Disabled Operating Automatic retry: tRETRY OCP_MODE = 1bnFAULT / I2C2DisabledOperating Automatic retry: tRETRY Automatic retry: tRETRY RETRY Thermal Shutdown (TSD) TJ > TTSD TSD_MODE = 0b nFAULT / I2C Disabled Operating Latched: CLR_FLT Thermal Shutdown (TSD)TJ > TTSD JTSD TSD_MODE = 0b TSD_MODE = 0b nFAULT / I2C nFAULT / I2C2DisabledOperatingLatched: CLR_FLT TSD_MODE = 1b nFAULT / I2C Disabled Operating Automatic: TJ < TTSD - THYS TSD_MODE = 1b TSD_MODE = 1bnFAULT / I2C2DisabledOperating Automatic: TJ < TTSD - THYS Automatic: TJ < TTSD - THYS JTSDHYS Overvoltage protection (OVP) OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD _ I2C when OUTx = Hi-Z Disabled Disabled Automatic: VVOUT - VVM < VSD Overvoltage protection (OVP)OUTx = Hi-Z or nSLEEP = 0; VVOUT - VVM > VSD VOUTVMSD_I2C when OUTx = Hi-Z2DisabledDisabledAutomatic: VVOUT - VVM < VSD VOUTVMSD Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence Programming I2C Communication The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Communication2 The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high. A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Using the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. The I2C interface allows control and monitoring of the DRV8234 by a microcontroller. The I2C bus consists of a data line (SDA) and a clock line (SCL) with off-chip pull-up resistors. When the bus is idle, both SDA and SCL lines are pulled high.22A leader device, usually a microcontroller or a digital signal processor, controls the bus. The leader is responsible for generating the SCL signal and device addresses. The leader also generates specific conditions that indicate the START and STOP of data transfer. A follower device receives and/or transmits data on the bus under control of the leader device. DRV8234 is a follower device. The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - The lower four bits of the device address are derived from the inputs from the pins A1 and A0, which can be tied to board level power supply for logic high, GND for logic low, or left open. These four address bits are latched into the device at power up, so cannot be changed dynamically. The upper address bits of the device address are fixed at 0x60h, so the device address is as follows - Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h Device Addresses A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A0 Pin A3A2A1A0 bits ADDRESS (WRITE) ADDRESS (READ) A1 Pin A1 PinA0 PinA3A2A1A0 bitsADDRESS (WRITE)ADDRESS (READ) 0 0 0000b 0x60h 0x61h 0 High-Z 0001b 0x62h 0x63h 0 1 0010b 0x64h 0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1 1000b 0x70h 0x71h 0 0 0000b 0x60h 0x61h 0 000000b0x60h0x61h 0 High-Z 0001b 0x62h 0x63h 0 0High-Z0001b0x62h0x63h 0 1 0010b 0x64h 0x65h 0 010010b0x64h0x65h High-Z 0 0011b 0x66h 0x67h High-Z High-Z0 0011b 0011b 0x66h 0x66h 0x67h 0x67h High-Z High-Z 0100b 0x68h 0x69h High-ZHigh-Z 0100b 0100b 0x68h 0x68h 0x69h 0x69h High-Z 1 0101b 0x6Ah 0x6Bh High-Z 1 1 0101b 0101b 0x6Ah 0x6Ah 0x6Bh 0x6Bh 1 0 0110b 0x6Ch 0x6Dh 1 10 0110b 0110b 0x6Ch 0x6Ch 0x6Dh 0x6Dh 1 High-Z 0111b 0x6Eh 0x6Fh 1 1High-Z 0111b 0111b 0x6Eh 0x6Eh 0x6Fh 0x6Fh 1 1 1000b 0x70h 0x71h 1 1 1 1 1000b 1000b 0x70h 0x70h 0x71h 0x71hUsing the A0 and A1 pins, up to 9 DRV8234 follower devices can be controlled by one I2C bus. The DRV8234 does not respond to the general call address. It is recommended to use a 2.2kΩ pull-up resistor for these pins. 2 I2C Write To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence I2C Write2 To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition. I2C Write Sequence To write on the I2C bus, the leader device sends a START condition on the bus with the address of the 7-bit follower device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the follower sends the acknowledge bit, the leader device then sends the register address of the register to be written. The follower device sends an acknowledge (ACK) signal again which notifies the leader device that the follower device is ready. After this process, the leader device sends 8-bit write data and terminates the transmission with a STOP condition.2 I2C Write Sequence I2C Write Sequence2 I2C Read To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read2 To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device. During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence To read from a follower device, the leader device must first communicate to the follower device which register will be read from. This communication is done by the leader starting the transmission similarly to the write process which is by setting the address with the R/W bit equal to 0b (signifying a write). The leader device then sends the register address of the register to be read from. When the follower device acknowledges this register address, the leader device sends a START condition again, followed by the follower address with the R/W bit set to 1b (signifying a read). After this process, the follower device acknowledges the read request and the leader device releases the SDA bus, but continues supplying the clock to the follower device.During this part of the transaction, the leader device becomes the leader-receiver, and the follower device becomes the follower-transmitter. The leader device continues sending out the clock pulses, but releases the SDA line so that the follower device can transmit data. At the end of the byte, the leader device sends a negative-acknowledge (NACK) signal, signaling to the follower device to stop communications and release the bus. The leader device then sends a STOP condition. I2C Read Sequence I2C Read Sequence2 Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Register Map The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value The following table lists the memory-mapped I2C registers for the DRV8234. The I2C registers are used to configure the DRV8234 and for device diagnostics.22 Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b. Do not modify reserved registers or addresses not listed in the register map (#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38). Writing to these registers can have unintended effects. For all reserved bits, the default value is 0b.#GUID-AFC1067F-9586-4B97-AEB0-1D1C80706EC3/T4934523-38 I2C Registers Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW I2C Registers2 Address Name 7 6 5 4 3 2 1 0 Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW Address Name 7 6 5 4 3 2 1 0 Access Address Name 7 6 5 4 3 2 1 0 Access AddressName76543210Access 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x01 RC_STATUS1 SPEED[7:0] R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x04 REG_STATUS1 VMTR[7:0] R 0x05 REG_STATUS2 IMTR[7:0] R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x15 RC_CTRL4 KMC[7:0] RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x00 FAULT FAULT RSVD STALL OCP OVP TSD NPOR CNT_DONE R 0x00FAULTFAULT RSVD RSVD STALL STALL OCP OCP OVP OVP TSD TSD NPOR NPOR CNT_DONE CNT_DONER 0x01 RC_STATUS1 SPEED[7:0] R 0x01 RC_STATUS1 RC_STATUS1 SPEED[7:0] SPEED[7:0]R 0x02 RC_STATUS2 RC_CNT[7:0] R 0x02 RC_STATUS2 RC_STATUS2 RC_CNT[7:0] RC_CNT[7:0]R 0x03 RC_STATUS3 RC_CNT[15:8] R 0x03 RC_STATUS3 RC_STATUS3RC_CNT[15:8]R 0x04 REG_STATUS1 VMTR[7:0] R 0x04 REG_STATUS1 REG_STATUS1VMTR[7:0]R 0x05 REG_STATUS2 IMTR[7:0] R 0x05 0x05 REG_STATUS2 REG_STATUS2IMTR[7:0]R 0x06 REG_STATUS3 RSVD IN_DUTY[5:0] R 0x06 0x06 REG_STATUS3 REG_STATUS3 RSVD RSVDIN_DUTY[5:0]R 0x09 CONFIG0 EN_OUT EN_OVP EN_STALL VSNS_SEL* RSVD CLR_CNT CLR_FLT DUTY_CTRL* RW 0x09 0x09 CONFIG0 CONFIG0EN_OUTEN_OVPEN_STALLVSNS_SEL*RSVD CLR_CNT CLR_CNT CLR_FLT CLR_FLTDUTY_CTRL*RW 0x0A CONFIG1 TINRUSH[7:0] RW 0x0A 0x0A CONFIG1 CONFIG1 TINRUSH[7:0] TINRUSH[7:0]RW 0x0B CONFIG2 TINRUSH[15:8] RW 0x0B 0x0B CONFIG2 CONFIG2TINRUSH[15:8] RW RW 0x0C CONFIG3 IMODE[1:0]* SMODE* INT_VREF* TBLANK* TDEG* OCP_MODE* TSD_MODE* RW 0x0C 0x0C CONFIG3 CONFIG3IMODE[1:0]*SMODE*INT_VREF* TBLANK* TBLANK* TDEG* TDEG*OCP_MODE*TSD_MODE*RW 0x0D CONFIG4 RC_REP[1:0] STALL_REP CBC_REP PMODE* I2C_BC* I2C_EN_IN1 I2C_PH_IN2 RW 0x0D 0x0D CONFIG4 CONFIG4RC_REP[1:0] STALL_REP STALL_REP CBC_REP CBC_REP PMODE* PMODE* I2C_BC* I2C_BC* I2C_EN_IN1 I2C_EN_IN1 I2C_PH_IN2 I2C_PH_IN2RW 0x0E REG_CTRL0 RSVD EN_SS REG_CTRL[1:0]* PWM_FREQ* W_SCALE[1:0] RW 0x0E 0x0EREG_CTRL0 RSVD RSVD EN_SS EN_SS REG_CTRL[1:0]* REG_CTRL[1:0]* PWM_FREQ* PWM_FREQ* W_SCALE[1:0] W_SCALE[1:0]RW 0x0F REG_CTRL1 WSET_VSET[7:0] RW 0x0F 0x0FREG_CTRL1 WSET_VSET[7:0] WSET_VSET[7:0]RW 0x10 REG_CTRL2 OUT_FLT[1:0] EXT_DUTY[5:0] RW 0x10 0x10 REG_CTRL2 REG_CTRL2 OUT_FLT[1:0] OUT_FLT[1:0] EXT_DUTY[5:0] EXT_DUTY[5:0] RW RW 0x11 RC_CTRL0 EN_RC DIS_EC RC_HIZ FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] RW 0x11 0x11 RC_CTRL0 RC_CTRL0 EN_RC EN_RC DIS_EC DIS_EC RC_HIZ RC_HIZ FLT_GAIN_SEL[1:0] FLT_GAIN_SEL[1:0] CS_GAIN_SEL[2:0] CS_GAIN_SEL[2:0]RW 0x12 RC_CTRL1 RC_THR[7:0] RW 0x12 0x12RC_CTRL1RC_THR[7:0]RW 0x13 RC_CTRL2 INV_R_SCALE[1:0] KMC_SCALE[1:0] RC_THR_SCALE[1:0] RC_THR[9:8] RW 0x13 0x13RC_CTRL2INV_R_SCALE[1:0] KMC_SCALE[1:0] KMC_SCALE[1:0]RC_THR_SCALE[1:0] RC_THR[9:8] RC_THR[9:8]RW 0x14 RC_CTRL3 INV_R[7:0] RW 0x14 0x14RC_CTRL3 INV_R[7:0] INV_R[7:0]RW 0x15 RC_CTRL4 KMC[7:0] RW 0x15 0x15 RC_CTRL4 RC_CTRL4 KMC[7:0] KMC[7:0] RW RW 0x16 RC_CTRL5 FLT_K[3:0] RSVD RW 0x16 0x16RC_CTRL5FLT_K[3:0] RSVD RSVDRW 0x17 RC_CTRL6 EC_PULSE_DIS T_MECH_FLT EC_FALSE_PER EC_MISS_PER RW 0x17 0x17 RC_CTRL6 RC_CTRL6EC_PULSE_DIST_MECH_FLTEC_FALSE_PEREC_MISS_PERRW 0x18 RC_CTRL7 KP_DIV[2:0] KP[4:0] RW 0x18RC_CTRL7KP_DIV[2:0]KP[4:0]RW 0x19 RC_CTRL8 KI_DIV[2:0] KI[4:0] RW 0x19RC_CTRL8KI_DIV[2:0]KI[4:0]RW *Writable only when EN_OUT=0. *Writable only when EN_OUT=0. Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_STATUS Registers lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_STATUS registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). DRV8234_STATUS Registers Offset Acronym Register Name Section 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 0h FAULT Various fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 0h FAULT Various fault registers' status. 0hFAULTVarious fault registers' status. 1h RC_STATUS1 Ripple Counting Status Registers - 1. 1hRC_STATUS1Ripple Counting Status Registers - 1. 2h RC_STATUS2 Ripple Counting Status Registers - 2. 2hRC_STATUS2Ripple Counting Status Registers - 2. 3h RC_STATUS3 Ripple Counting Status Registers - 3. 3hRC_STATUS3Ripple Counting Status Registers - 3. 4h REG_STATUS1 Regulation Status Registers - (1/3). 4hREG_STATUS1Regulation Status Registers - (1/3). 5h REG_STATUS2 Regulation Status Registers - (2/3). 5hREG_STATUS2Regulation Status Registers - (2/3). 6h REG_STATUS3 Regulation Status Registers - (3/3). 6hREG_STATUS3Regulation Status Registers - (3/3). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8234_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in . Return to the Summary Table. Status of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register (Offset = 0h) [Reset = 00h] FAULT is shown in .Return to the Summary Table.Summary TableStatus of various fault and protection bits. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. FAULT Register Field Descriptions Bit Field Type Reset Description 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 7 FAULT R 0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 7FAULTR0h 0b during normal operation, 1b during a fault condition. nFAULT pin is pulled down when FAULT bit is 1b. nFAULT pin is released during normal operation. 6 RSVD R 0h Reserved. 6RSVDR0h Reserved. 5 STALL R 0h When this bit is 1b, it indicates motor stall. 5STALLR0h When this bit is 1b, it indicates motor stall. 4 OCP R 0h 0b during normal operation, 1b if OCP event occurs. 4OCPR0h 0b during normal operation, 1b if OCP event occurs. 3 OVP R 0h 0b during normal operation, 1b if OVP event occurs. 3OVPR0h 0b during normal operation, 1b if OVP event occurs. 2 TSD R 0h 0b during normal operation, 1b if TSD event occurs. 2TSDR0h 0b during normal operation, 1b if TSD event occurs. 1 NPOR R 0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 1NPORR0h Reset and latched low if VM>VUVLO. Remains reset until the CLR_FLT bit is set to issue a clear fault command. After power up, automatically latched high once CLR_FLT command is issued. Refer to for further explanation. 0 CNT_DONE R 0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. 0CNT_DONER0h Status flag. Latched high when RC_CNT exceeds the ripple counting threshold. Can be cleared by CLR_CNT command. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in . Return to the Summary Table. Speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register (Offset = 1h) [Reset = 00h] RC_STATUS1 is shown in .Return to the Summary Table.Summary TableSpeed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0 SPEED R 0h Outputs the motor speed estimated by the ripple counting algorithm. 7-0SPEEDR0h Outputs the motor speed estimated by the ripple counting algorithm. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register (Offset = 2h) [Reset = 00h] RC_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (1/2). RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_7:0 R 0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_7:0R0h Lower half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in . Return to the Summary Table. Output corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register (Offset = 3h) [Reset = 00h] RC_STATUS3 is shown in .Return to the Summary Table.Summary TableOutput corresponding to number of current ripples (2/2). RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. RC_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0 RC_CNT_15:8 R 0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. 7-0RC_CNT_15:8R0h Upper half 8-bit output out of the 16-bit output of the ripple counter corresponding to the number of current ripples. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in . Return to the Summary Table. Value corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register (Offset = 4h) [Reset = 00h] REG_STATUS1 is shown in .Return to the Summary Table.Summary TableValue corresponding to the output voltage across the motor terminals. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0 VMTR R 0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. 7-0VMTRR0h Outputs the voltage across the motor terminals, maximum value FFh. 00h corresponds to 0 V and E4h corresponds to 38 V. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in . Return to the Summary Table. Output corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register (Offset = 5h) [Reset = 00h] REG_STATUS2 is shown in .Return to the Summary Table.Summary TableOutput corresponding to current flowing through the motor. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0 IMTR R 0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. 7-0IMTRR0h Outputs the current flowing through the motor. 00h corresponds to 0 A and C0h corresponds to the maximum value set by the CS_GAIN_SEL bits. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in . Return to the Summary Table. Internal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register (Offset = 6h) [Reset = 00h] REG_STATUS3 is shown in .Return to the Summary Table.Summary TableInternal pwm duty cycle and device id. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. REG_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5-0 IN_DUTY R 0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. 5-0IN_DUTYR0h Represents the bridge control duty cycle generated by an internal regulation logic. This register is applicable when speed or voltage regulation is activated. When speed or voltage regulation is inactive, set DUTY_CTRL to 1b and program the duty cycle in EXT_DUTY explained later. The range of duty cycle is 0% (000000b) to 100% (111111b). Refer to for further explanation on the internal PWM generation scheme. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CONFIG Registers lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CONFIG registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DRV8234_CONFIG Registers Offset Acronym Register Name Section 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection 9h CONFIG0 Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). 9h CONFIG0 Configuration Registers - Faults (1/5). 9hCONFIG0Configuration Registers - Faults (1/5). Ah CONFIG1 Configuration Registers - (2/5). AhCONFIG1Configuration Registers - (2/5). Bh CONFIG2 Configuration Registers - (3/5). BhCONFIG2Configuration Registers - (3/5). Ch CONFIG3 Configuration Registers - (4/5). ChCONFIG3Configuration Registers - (4/5). Dh CONFIG4 Configuration Registers - (5/5). DhCONFIG4Configuration Registers - (5/5). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CONFIG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in . Return to the Summary Table. Enable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register (Offset = 9h) [Reset = 60h] CONFIG0 is shown in .Return to the Summary Table.Summary TableEnable/Disable various faults like OCP, OVP, STALL, etc. CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG0 Register Field Descriptions Bit Field Type Reset Description 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 7 EN_OUT R/W 0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 7EN_OUTR/W0h 0b: All driver FETs are Hi-Z. 1b: Enables the driver outputs. 6 EN_OVP R/W 1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 6EN_OVPR/W1h Enables the OVP feature. 1b by default, can be made 0b after power-up to disable the OVP feature. Refer to for further explanation. 5 EN_STALL R/W 1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 5EN_STALLR/W1h Enables the Stall Detection feature. Stall detection feature can be disabled by setting this bit to 0b. Refer to EN_STALL configuration under for further explanation. 4 VSNS_SEL R/W 0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 4VSNS_SELR/W0h 0b: Use the analog low-pass filter to average out the output voltage for voltage regulation. Refer to OUT_FLT for further description of the analog low-pass filter. 0b is the recommended value. 1b: Use the digital low-pass filter for voltage regulation. This option perfroms multiplication of the duty cycle with VM to obtain the output voltage. 3 RSVD R 0h Reserved 3RSVDR0h Reserved 2 CLR_CNT R/W 0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 2CLR_CNTR/W0h Resets the ripple counter to 0, and resets CNT_DONE. Also releases nFAULT when RC_REP = 10b. CLR_CNT is automatically reset. 1 CLR_FLT R/W 0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 1CLR_FLTR/W0h Clears all latched faults when set to 1b. CLR_FLT is automatically reset. 0 DUTY_CTRL R/W 0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). 0DUTY_CTRLR/W0h When speed regulation is disabled and the DUTY_CTRL bit is 1b, user can write desired PWM duty to EXT_DUTY bits. The range of duty is 0% (000000b) to 100% (111111b). CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in . Return to the Summary Table. Configure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register (Offset = Ah) [Reset = 00h] CONFIG1 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (1/2). CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG1 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_7:0 R/W 0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_7:0R/W0h Lower half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in . Return to the Summary Table. Configure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register (Offset = Bh) [Reset = 00h] CONFIG2 is shown in .Return to the Summary Table.Summary TableConfigure the inrush time (2/2). CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG2 Register Field Descriptions Bit Field Type Reset Description 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0 TINRUSH_15:8 R/W 0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. 7-0TINRUSH_15:8R/W0h Upper half 8-bit output out of the total 16-bit output for inrush time blanking for stall detection. Sets the amount of time for which the stall detection scheme ignores motor inrush current. Refer to for further explanation. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in . Return to the Summary Table. Enable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register (Offset = Ch) [Reset = 63h] CONFIG3 is shown in .Return to the Summary Table.Summary TableEnable/Disable various device modes like IMODE, SMODE and parameters like blanking time. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. CONFIG3 Register Field Descriptions Bit Field Type Reset Description 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 7-6 IMODE R/W 1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 7-6IMODER/W1h Determines the behavior of current regulation. Refer to IMODE configuration under for further explanation. 5 SMODE R/W 1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 5SMODER/W1h Programs device response to a stall condition. Refer to SMODE configuration under for further explanation. 4 INT_VREF R/W 0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 4INT_VREFR/W0h If set to 1b, sets VREF voltage to 3 V internally. Voltage is not fixed if INT_VREF is set to 0b. Refer to for further explanation. 3 TBLANK R/W 0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs. 3TBLANKR/W0h Sets the current sense blanking time. If set to 0b, tBLANK=1.8µs. If set to 1b, tBLANK=1.0µs.BLANKBLANK 2 TDEG R/W 0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs. 2TDEGR/W0h Sets the current regulation and stall detection deglitch time. If set to 0b, tDEG=2µs. If set to 1b, tDEG=1µs.DEGDEG 1 OCP_MODE R/W 1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 1OCP_MODER/W1h Programs device response to an overcurrent event. If set to 0b, device is latched off in case of an OCP event. Can be cleared using CLR_FLT. If set to 1b, device performs auto-retry after time tretry in case of an OCP event. Refer to for further explanation. 0 TSD_MODE R/W 1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS. 0TSD_MODER/W1h Programs device response to an overtemperature event. If set to 0b, device is latched off in case of a TSD event. If set to 1b, device performs auto-retry when TJ<TTSD–THYS.JTSDHYS CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in . Return to the Summary Table. Configure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register (Offset = Dh) [Reset = 38h] CONFIG4 is shown in .Return to the Summary Table.Summary TableConfigure the report registers like RC_REP and STALL_REP. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. CONFIG4 Register Field Descriptions Bit Field Type Reset Description 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 7-6 RC_REP R/W 0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation. 7-6RC_REPR/W0h Determines whether nFAULT is pulled low when RC_CNT exceeds threshold, and the behavior of RC_CNT when it reaches maximum value of (216-1). Refer to RC_REP Settings under for further explanation.16 5 STALL_REP R/W 1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 5STALL_REPR/W1h Determines whether stall is reported on the nFAULT pin. When set to 1b, nFAULT is low whenever stall is detected. When set to 0b, stall is not reported on nFAULT output. Refer to for further explanation. 4 CBC_REP R/W 1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 4CBC_REPR/W1h When REG_CTRL is set to 01b, the device enters cycle-by-cycle mode of current regulation. In this mode, the device can indicate whenever the H-bridge enters internal current regulation. CBC_REP bit is used to determine device outputs' behavior in the cycle-by-cycle mode. 1b: nFAULT is pulled low when H-Bridge enters internal current regulation. 0b: nFAULT is not pulled low when H-Bridge enters internal current regulation. Refer to for further explanation. 3 PMODE R/W 1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 3PMODER/W1h Switch between phase/enable mode and PWM mode. 0b: PH/EN. 1b: PWM. 2 I2C_BC R/W 0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 2I2C_BCR/W0h Decides the H-Bridge Control Interface. 0b: Bridge control configured by INx pins. 1b: Bridge control configured by I2C bits I2C_EN_IN1 and I2C_PH_IN2. 1 I2C_EN_IN1 R/W 0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 1I2C_EN_IN1R/W0h Enable/PWM Input Bit 1 for internal bridge control. Used when I2C_BC=1b. Ignored when I2C_BC=0b. 0 I2C_PH_IN2 R/W 0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. 0I2C_PH_IN2R/W0h Phase/PWM Input Bit 2 for internal bridge control. Used when I2C_BC=1b.Ignored when I2C_BC=0b. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. DRV8234_CTRL Registers lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value lists the memory-mapped registers for the DRV8234_CTRL registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified. DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). DRV8234_CTRL Registers Offset Acronym Register Name Section Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Offset Acronym Register Name Section Offset Acronym Register Name Section OffsetAcronymRegister NameSection Eh REG_CTRL0 Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). Eh REG_CTRL0 Regulation control registers (1/3). EhREG_CTRL0Regulation control registers (1/3). Fh REG_CTRL1 Regulation control registers (2/3). FhREG_CTRL1Regulation control registers (2/3). 10h REG_CTRL2 Regulation control registers (3/3). 10hREG_CTRL2Regulation control registers (3/3). 11h RC_CTRL0 Ripple Counting Control Registers - (1/9). 11hRC_CTRL0Ripple Counting Control Registers - (1/9). 12h RC_CTRL1 Ripple Counting Control Registers - (2/9). 12hRC_CTRL1Ripple Counting Control Registers - (2/9). 13h RC_CTRL2 Ripple Counting Control Registers - (3/9). 13hRC_CTRL2Ripple Counting Control Registers - (3/9). 14h RC_CTRL3 Ripple Counting Control Registers - (4/9). 14hRC_CTRL3Ripple Counting Control Registers - (4/9). 15h RC_CTRL4 Ripple Counting Control Registers - (5/9). 15hRC_CTRL4Ripple Counting Control Registers - (5/9). 16h RC_CTRL5 Ripple Counting Control Registers - (6/9). 16hRC_CTRL5Ripple Counting Control Registers - (6/9). 17h RC_CTRL6 Ripple Counting Control Registers - (7/9). 17hRC_CTRL6Ripple Counting Control Registers - (7/9). 18h RC_CTRL7 Ripple Counting Control Registers - (8/9). 18hRC_CTRL7Ripple Counting Control Registers - (8/9). 19h RC_CTRL8 Ripple Counting Control Registers - (9/9). 19hRC_CTRL8Ripple Counting Control Registers - (9/9). Complex bit access types are encoded to fit into small table cells. shows the codes that are used for access types in this section. DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value DRV8234_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Access Type Code Description Access Type Code Description Access TypeCodeDescription Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value Read Type Read Type R R Read RRRead Write Type Write Type W W Write WWWrite Reset or Default Value Reset or Default Value -n Value after reset or the default value -n nValue after reset or the default value REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in . Return to the Summary Table. Set features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register (Offset = Eh) [Reset = 27h] REG_CTRL0 is shown in .Return to the Summary Table.Summary TableSet features like Soft Start/Stop, speed scaling factor, etc. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 RSVD R 0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 7-6 RSVD R 0h Reserved. 7-6RSVDR0h Reserved. 5 EN_SS R/W 1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation. 5EN_SSR/W1h Used to enable/disable soft start/stop. 1b: Target motor voltage or speed is soft-started and soft-stopped over the duration of tINRUSH time. 0b: Soft-start/stop feature is disabled. Refer to for further explanation.INRUSH 4-3 REG_CTRL R/W 0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 4-3REG_CTRLR/W0h Selects the current regulation scheme (fixed off-time or cycle-by-cycle) or motor speed and voltage regulation. 00b: Fixed Off-Time Current Regulation. 01b: Cycle-By-Cycle Current Regulation. 10b: Motor speed is regulated. Ripple counting must be enabled in this mode by setting EN_RC to 1b. 11b: Motor voltage is regulated. Refer to for further explanation. 2 PWM_FREQ R/W 1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 2PWM_FREQR/W1h Sets the PWM frequency when bridge control is configured by INx bits (I2C_BC=1b). 0b: PWM frequency is set to 50kHz. 1b: PWM frequency is set to 25kHz. 1-0 W_SCALE R/W 3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. 1-0W_SCALER/W3h Scaling factor that helps in setting the target ripple speed. 00b: 16 01b: 32 10b: 64 11b: 128 Refer to for further explanation. REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in . Return to the Summary Table. Set the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register (Offset = Fh) [Reset = FFh] REG_CTRL1 is shown in .Return to the Summary Table.Summary TableSet the target motor voltage and speed. REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0 WSET_VSET R/W FFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . 7-0WSET_VSETR/WFFh Sets the target motor voltage or ripple speed. A detailed explanation is provided in . REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in . Return to the Summary Table. Set the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register (Offset = 10h) [Reset = 00h] REG_CTRL2 is shown in .Return to the Summary Table.Summary TableSet the duty cycle and cut-off frequency for output voltage filtering. REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). REG_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 7-6 OUT_FLT R/W 0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 7-6OUT_FLTR/W0h Programs the cut-off frequency of the output voltage filtering. 00b: 250Hz 01b: 500Hz 10b: 750Hz 11b: 1000Hz For best results, choose a cut-off frequency equal to a value at least 20 times lower than the PWM frequency. Eg, if you PWM at 20kHz, OUT_FLT=11b (1000Hz) is sufficient. 5-0 EXT_DUTY R/W 0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). 5-0EXT_DUTYR/W0h Available when using external bridge control (I2C_BC=0b). DUTY_CTRL must be set to 1b. Speed and voltage regulation modes are inactive in this case. User can program the desired duty cycle in the EXT_DUTY bits. The range of duty cycle is 0% (000000b) to 100% (111111b). RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in . Return to the Summary Table. Set various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register (Offset = 11h) [Reset = 88h] RC_CTRL0 is shown in .Return to the Summary Table.Summary TableSet various functions for RC including enable/disable. RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL0 Register Field Descriptions Bit Field Type Reset Description 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 7 EN_RC R/W 1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 7EN_RCR/W1h Enable/Disable Ripple Counting. 0b: Disable 1b: Enable 6 DIS_EC R/W 0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 6DIS_ECR/W0h Enable/Disable the Error Correction module. 0b: Error Correction is enabled. 1b: Error Correction is disabled. Please note that this is different from the EC_PULSE_DIS described earlier. 5 RC_HIZ R/W 0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 5RC_HIZR/W0h 0b: H-bridge stays enabled when RC_CNT exceeds threshold. 1b: H-bridge is disabled (High-Z) when RC_CNT exceeds threshold. 4-3 FLT_GAIN_SEL R/W 1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 4-3FLT_GAIN_SELR/W1h Filter input scaling factor. This factor scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. The options are: 00b: 2 01b: 4 10b: 8 11b: 16 Refer to for further explanation. 2-0 CS_GAIN_SEL R/W 0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A 2-0CS_GAIN_SELR/W0h Used to select the current scaling options. Settings are as follows: X00b: 4 A X01b: 2 A X10b: 1 A X11b: 0.5 A RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in . Return to the Summary Table. Threshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register (Offset = 12h) [Reset = FFh] RC_CTRL1 is shown in .Return to the Summary Table.Summary TableThreshold for ripple counting. RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0 RC_THR R/W FFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-0RC_THRR/WFFh Lower 8 bits of the 10-bit RC_THR Register. Threshold level to compare against the RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in . Return to the Summary Table. Set values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register (Offset = 13h) [Reset = 7Fh] RC_CTRL2 is shown in .Return to the Summary Table.Summary TableSet values of various scaling parameters. RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 7-6 INV_R_SCALE R/W 1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 7-6INV_R_SCALER/W1h Scaling factor for the INV_R parameter. 00b: INV_R_SCALE = 2 01b: INV_R_SCALE = 64 10b: INV_R_SCALE = 1024 11b: INV_R_SCALE = 8192 Refer to for further explanation. 5-4 KMC_SCALE R/W 3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation. 5-4KMC_SCALER/W3h Scaling factor for KMC parameter. 00b: KMC_SCALE = 24 x 28 01b: KMC_SCALE = 24 x 29 10b: KMC_SCALE = 24 x 212 11b: KMC_SCALE = 24 x 213 Refer to for further explanation.891213 3-2 RC_THR_SCALE R/W 3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 3-2RC_THR_SCALER/W3h Scaling factor for RC_THR. 00b: RC_THR_SCALE = 2 01b: RC_THR_SCALE = 8 10b: RC_THR_SCALE = 16 11b: RC_THR_SCALE = 64 1-0 RC_THR_9:8 R/W 3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE 1-0RC_THR_9:8R/W3h Upper two bits of the 10-bit RC_THR Register. Threshold level to compare against RC_CNT based on the expected time of motor actuation. Ripple counting threshold = RC_THR x RC_THR_SCALE RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in . Return to the Summary Table. Set the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register (Offset = 14h) [Reset = 00h] RC_CTRL3 is shown in .Return to the Summary Table.Summary TableSet the INV_R parameter. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0 INV_R R/W 0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. 7-0INV_RR/W0h User input based on motor coil resistance. INV_R = INV_R_SCALE / Motor Resistance. Must not be set to 0. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in . Return to the Summary Table. Set the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register (Offset = 15h) [Reset = 00h] RC_CTRL4 is shown in .Return to the Summary Table.Summary TableSet the KMC parameter. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. RC_CTRL4 Register Field Descriptions Bit Field Type Reset Description 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0 KMC R/W 0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation. 7-0KMCR/W0h Represents a proportional value of the motor back emf constant. KMC = (KV) / NR)*KMC_SCALE. Refer to for further explanation.VR RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in . Return to the Summary Table. Set the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register (Offset = 16h) [Reset = 00h] RC_CTRL5 is shown in .Return to the Summary Table.Summary TableSet the filter damping constant. RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved RC_CTRL5 Register Field Descriptions Bit Field Type Reset Description 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 7-4 FLT_K R/W 0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 7-4FLT_KR/W0h Bandpass filter 1/Q factor. Sets the bandwidth of the bandpass filter. Recommended value is the default value: 6d. Refer to for further explanation. 3-0 RSVD R 0h Reserved 3-0RSVDR0h Reserved RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in . Return to the Summary Table. Disable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register (Offset = 17h) [Reset = 45h] RC_CTRL6 is shown in .Return to the Summary Table.Summary TableDisable the Error Correction pulses for Ripple Counting. RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL6 Register Field Descriptions Bit Field Type Reset Description 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 7 EC_PULSE_DIS R/W 0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 7EC_PULSE_DISR/W0h Disable the Error Correction Pulses. Differs from the EN_EC bit described previously. 0b: Error correction is always enabled. 1b: Error correction will stop giving pulses under certain conditions described in . 6-4 T_MECH_FLT R/W 4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system. Increase this value to for a slower response and decrease it for a faster response. 3-2 EC_FALSE_PER R/W 1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0 EC_MISS_PER R/W 1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% 1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple. 00b: 20% 01b: 30% 10b: 40% 11b: 50% RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in . Return to the Summary Table. Set the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register (Offset = 18h) [Reset = 21h] RC_CTRL7 is shown in .Return to the Summary Table.Summary TableSet the proportional constant in PI control loop. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL7 Register Field Descriptions Bit Field Type Reset Description 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 7-5 KP_DIV R/W 1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop. Actual proportional constant = KP/KP_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KP R/W 1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. 4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register. Actual Proportional Constant = KP/KP_DIV. For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence, Actual proportional constant = 1/16 = 0.0625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in . Return to the Summary Table. Set the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register (Offset = 19h) [Reset = 21h] RC_CTRL8 is shown in .Return to the Summary Table.Summary TableSet the integral constant in PI control loop. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. RC_CTRL8 Register Field Descriptions Bit Field Type Reset Description 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Bit Field Type Reset Description Bit Field Type Reset Description BitFieldTypeResetDescription 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 7-5 KI_DIV R/W 1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop. Actual integral constant = KI/KI_DIV. Settings are as follows: 000b: 32 001b: 64 010b: 128 011b: 256 100b: 512 101b: 16 110b: 1 4-0 KI R/W 1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. 4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register. Actual Integral Constant = KI/KI_DIV. For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence, Actual integral constant = 29/32 = 0.90625. Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8234 is intended to drive one brushed DC motor. Application Information The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. The DRV8234 is intended to drive one brushed DC motor. Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Typical Application: Brushed DC Motor A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled A typical application for the DRV8234 is to drive a brushed DC motor using the full-bridge outputs. shows a schematic example. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections with stall detection disabled Typical Connections with stall detection disabled Typical Connections with stall detection disabled Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Requirements #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF #GUID-6F4A8C1E-810B-49EA-89A6-55DBE0B25852/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Bulk Capacitance CBULK 50μF Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2. A Motor inrush (startup) currentIINRUSH INRUSH 2. A 2. A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Bulk Capacitance CBULK 50μF Bulk CapacitanceCBULK BULK50μF Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8234 supports hardware stall detection by comparing the IPROPI pin voltage to the VREF pin voltage or 3 V as applicable. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature. Example timing diagram for stall detection The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8234 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The TINRUSH register sets the timing, tINRUSH, so the DRV8234 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8234 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nFAULT pin becomes low and the appropriate registers indicate stall to the microcontroller using the I2C pins. provides all the details for configuring the stall detection feature.INRUSH2 Example timing diagram for stall detection Example timing diagram for stall detection Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8234 uses the TINRUSH register to ignore the inrush current during the startup time, tINRUSH. describes the overall details for using the stall detection feature.INRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8234 and the system overall. INRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. TRIPTRIPVM Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Ripple Counting Application This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. This section describes Ripple Counting and the associated tuning procedure using an example. Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Tuning Ripple Counting Parameters This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . This section explains the tuning process for the Ripple Counting parameters described in . Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Resistance Parameters This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E For example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). This section describes how to select INV_R and INV_R_SCALE. The first step is to find the motor resistance. This can be done in three ways: Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below. Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance. Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above. Use the motor resistance value mentioned in the data sheet of the motor. If this is not available, use one of the other methods listed below.Perform a voltage sweep at the motor terminals, stall the motor at each voltage level, and measure the motor current. Please note that at least 10 measurements are required at every voltage level whilst rotating the motor by approximately 30° for each measurement. This is because it is unknown if the commutator segments are in contact with the brushes in a particular motor position which renders a lower, incorrect motor resistance value. If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance. Take the average of all values to calculate motor resistance.If motor resistance from the motor's data sheet is unavailable, then this method is recommended to obtain the value of motor resistance.Measure the motor resistance using a digital multimeter. Please note that this process also needs to be done at every voltage level for 10 measurements each and then averaged out at the end for the same reason as mentioned above.Once the motor resistance value is found, select an appropriate value of INV_R_SCALE and calculate INV_R. The formula to calculate INV_R is: I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E I N V _ R   = 1 M o t o r   R e s i s t a n c e × I N V _ R _ S C A L E INV_R = 1 M o t o r   R e s i s t a n c e 1 1 M o t o r   R e s i s t a n c e Motor Resistance×INV_R_SCALEFor example, if the motor resistance is 25 Ω, we have the following possible results based on the choice of INV_R_SCALE: Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 25 Ω Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Selection Example for INV_R_SCALE and INV_R Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment Bit INV_R_SCALE value INV_R_SCALE/Motor Resistance(Actual Value) Rounded ValueINV_R Comment BitINV_R_SCALE valueINV_R_SCALE/Motor Resistance(Actual Value) (Actual Value)Rounded ValueINV_R INV_RComment 00b 2 2/25=0.08 0 Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 00b 2 2/25=0.08 0 Do not select, since output is 0. 00b22/25=0.080Do not select, since output is 0. 01b 64 64/25=2.56 3 Avoid selecting, since low bit precision. 01b6464/25=2.563Avoid selecting, since low bit precision. 10b 1024 1024/25=40.96 41 Can select this value. 10b 10b 1024 1024 1024/25=40.96 1024/25=40.96 41 41 Can select this value. Can select this value. 11b 8192 8192/25=327.68 328 Cannot select this value because 328 exceeds the maximum limit for INV_R (255). 11b81928192/25=327.68328Cannot select this value because 328 exceeds the maximum limit for INV_R (255). KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. KMC and KMC_SCALE Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Selection of KMC_SCALE and KMC can be divided into two cases based on : Value of the motor back emf constant, KV is known to the user from the data sheet of the motor. Value of the motor back emf constant, KV is unknown to the user. Value of the motor back emf constant, KV is known to the user from the data sheet of the motor.VValue of the motor back emf constant, KV is unknown to the user.V Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Case I In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options: Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. In case 1, can be used. Choose the value of KMC_SCALE such that KMC is within the range of 0 to 255 with highest bit resolution. As an example, if KV= 0.01 and number of ripples per revolution, NR=10, KV/NR = 10-3. The following table lists the available options:VRVR-3 Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Selection Example for KMC_SCALE Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment Bit KMC_SCALE value KV/NRx KMC_SCALE (Actual Value) Rounded Value(KMC) Comment BitKMC_SCALE value KV/NRx KMC_SCALE (Actual Value) KV/NRx KMC_SCALEVR(Actual Value)Rounded Value(KMC) (KMC)Comment 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 00b 24 x 28 6.144 6 Avoid selecting, since low bit precision. 00b24 x 28 86.1446Avoid selecting, since low bit precision. 01b 24 x 29 12.288 12 Avoid selecting, since low bit precision. 01b24 x 29 912.28812Avoid selecting, since low bit precision. 10b 24 x 212 98.304 98 Avoid selecting, since low bit precision. 10b24 x 212 1298.30498Avoid selecting, since low bit precision. 11b 24 x 213 196.608 197 Can select this value as this has the highest bit precision. 11b 11b 24 x 213 24 x 213 13 196.608 196.608 197 197 Can select this value as this has the highest bit precision. Can select this value as this has the highest bit precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Case II In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: In case 2, KMC and KMC_SCALE need to be tuned manually using either of the two methods: Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 1: Tuning from Scratch This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in This method resets both parameters in the beginning before arriving at tuned values. displays a flowchart for tuning KMC_SCALE using this method. KMC can be found using Binary Search as shown in Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Tuning KMC_SCALE Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Select the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255. Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s. Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED. If EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit. Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED. Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. Obtain the value of actual ripple speed in rad/s using either of the two methods: Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Where NR is the number of ripples per revolution. Let this value be called OBS_SPEED. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Use a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9. Use an oscilloscope to observe motor current waveform to measure the ripple frequency. This can be done in two ways: Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. The frequency of ripples is observed in Hz on the oscilloscope. Please consider at least 20 ripples while calculating frequency. Divide the number of ripples by the time taken for calculating the frequency in Hz. Convert into rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7. Please note that this is the recommended method. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe. Through the IPROPI pin which provides an output proportional to the motor current. Through a current probe.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-AE15E2EF-04EC-4656-93E5-C50543F85CA7this is the recommended methodUse a tachometer to obtain the motor speed in rpm. Convert the motor speed into ripple speed using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806. Finally, convert the ripple speed in rpm to ripple speed in rad/s using #GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9.#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-DA1CB8AB-8016-4A98-AA4D-DEABD38FB806#GUID-EC1DF9FC-D046-4DDD-99B5-B294445BED27/GUID-727B7DFE-24A1-4965-B16C-1A3E084C26E9 R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R R i p p l e   S p e e d = M o t o r   S p e e d × N R Ripple Speed=Motor Speed× N R N N R R R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   H z ) × 2 π Ripple Speed (in rad/s)=Ripple Speed (in Hz)×2π R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 R i p p l e   S p e e d   ( i n   r a d / s ) = R i p p l e   S p e e d   ( i n   r p m ) × 2 π 60 Ripple Speed (in rad/s)=Ripple Speed (in rpm)× 2 π 60 2 π 2π 60 60RSelect the lowest value of KMC_SCALE, 00b. Set KMC to the highest possible value, 255.Refer to to set W_SCALE to a value where maximum ripple speed is more than OBS_SPEED. For example, if OBS_SPEED is 6000 rad/s, set W_SCALE to 01b allowing a maximum speed of 8160 rad/s.Convert the ripple speed on the SPEED register into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Let this value be called EST_SPEED.SPEEDSPEEDW_SCALEIf EST_SPEED is lower than OBS_SPEED, increase KMC_SCALE by one bit.Repeat steps 4-5 until EST_SPEED is higher than OBS_SPEED.Set KMC_SCALE to the previous value. For example, if 11b was obtained in the previous step, set KMC_SCALE to 10b. This is the tuned value of KMC_SCALE. KMC_SCALE Tuning Procedure KMC_SCALE Tuning Procedure Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning KMC Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process. Let START = 0 and END = 255. Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure. If EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process. Let MID = (START+END)/2, rounded off to the nearest integer. If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC. If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Verify that EST_SPEED < OBS_SPEED and value of KMC is 255. If this is not the case, please restart the tuning process.Let START = 0 and END = 255.Set KMC to START and obtain the value of OBS_SPEED in rad/s from step 1 of the KMC_SCALE tuning procedure.from step 1 of the KMC_SCALE tuning procedureIf EST_SPEED is within OBS_SPEED ± W_SCALE value from , stop the tuning process and record the value of KMC. For example, if W_SCALE = 10b (corresponds to 64 rad/s), OBS_SPEED = 6000 rad/s, and EST_SPEED = 5937 rad/s, stop the tuning process.Let MID = (START+END)/2, rounded off to the nearest integer.If EST_SPEED is higher than OBS_SPEED in this step, set KMC to MID. If EST_SPEED is lower than OBS_SPEED in this step, decrement KMC_SCALE by one bit and repeat the binary search procedure to tune KMC.If EST_SPEED is higher than OBS_SPEED, update START = MID. If EST_SPEED is lower than OBS_SPEED, update END = MID. Repeat steps 4-7 until EST_SPEED is within OBS_SPEED ± W_SCALE value from . Record the value of KMC. Binary Search Algorithm to Find KMC Binary Search Algorithm to Find KMC Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Tuning is not possible in the following cases: EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), or EST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0). EST_SPEED is higher than OBS_SPEED after step 4 in the KMC_SCALE tuning process (KMC_SCALE = 00b; KMC = 255), orEST_SPEED is lower than OBS_SPEED after step 3 in the Binary Search Method for KMC (KMC_SCALE = 11b, KMC = 0).Multiple sets of KMC and KMC_SCALE exist. If found, then choose the set with highest bit resolution. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Method 2: Using the Proportionality factor This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have: ω r i p p l e = k d K M C _ S C A L E K M C Using the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f Using the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d Taking the ratio of the two equations above, the dummy constant, kd, cancels out: ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f At this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s. Plugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. This method utilises the factor of proportionality that associates KMC and KMC_SCALE with the ripple speed, ωripple. ωripple is directly proportional to KMC_SCALE but varies inversely with KMC. Let kd be a dummy constant. We have:ripplerippled ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e = k d K M C _ S C A L E K M C ω r i p p l e ω ω r i p p l e ripple= k d k k d d K M C _ S C A L E K M C K M C _ S C A L E KMC_SCALE K M C KMCUsing the subscript 'def' to denote default, we have the following equation for default values of KMC and KMC_SCALE: ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f = k d K M C _ S C A L E d e f K M C d e f ω d e f ω ω d e f def= k d k k d d K M C _ S C A L E d e f K M C d e f K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f def K M C d e f K M C d e f K M C KMC d e f defUsing the subscript 'tuned', we similarly have the following equation for tuned values of KMC and KMC_SCALE: ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d = k d K M C _ S C A L E t u n e d K M C t u n e d ω t u n e d ω ω t u n e d tuned= k d k k d d K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tunedTaking the ratio of the two equations above, the dummy constant, kd, cancels out:d ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f = K M C _ S C A L E t u n e d K M C t u n e d × K M C d e f K M C _ S C A L E d e f ω t u n e d ω d e f ω t u n e d ω t u n e d ω ω t u n e d tuned ω d e f ω d e f ω ω d e f def= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× K M C d e f K M C _ S C A L E d e f K M C d e f K M C d e f K M C KMC d e f def K M C _ S C A L E d e f K M C _ S C A L E d e f K M C _ S C A L E KMC_SCALE d e f defAt this point, the following is known: KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map. KMCdef = 163 is the default value of KMC from the register map. ωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. KMC_SCALEdef = 11b (24 x 213) is the default value of KMC_SCALE from the register map.def13KMCdef = 163 is the default value of KMC from the register map.defωtuned is the actual value of the ripple speed in rad/s. Please refer to step 1 of the KMC_SCALE Tuning Method 1 for obtaining this value. tunedKMC_SCALE Tuning Method 1To obtain ωdef, select a value of W_SCALE based on step 3 of KMC_SCALE Tuning Method 1. Next, convert the ripple speed on the SPEED register obtained using KMC_SCALEdef and KMCdef into rad/s by multiplying SPEED with W_SCALE. For example, if SPEED reads 0x04 and W_SCALE is set to 10b (corresponds to 64 rad/s), then ripple speed in rad/s = 4*64 = 256 rad/s.defKMC_SCALE Tuning Method 1SPEEDdefdefSPEEDW_SCALEPlugging the four values above and simplifying, we get a ratio of KMC_SCALEtuned and KMCtuned as a constant number. Select KMC_SCALEtuned from the four available values such that KMCtuned has the highest bit precision within limits (0 to 255). A working example is shown below. tunedtunedtunedtuned Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Working Example As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. As a working example, let ωtuned= 500 rad/s. Thus, W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: tuned W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on . Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s. Plugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have: W_SCALE is chosen as 00b (16 rad/s) since 500 < 4080, the maximum value allowable by W_SCALE based on .Let SPEED = 0x30. Thus, ωdef=48*16=768 rad/s.defPlugging these values into #GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D, we have:#GUID-44B4392F-7ABA-43DC-A11F-DBB9802DF777/GUID-D0B11C8B-F020-4132-B57C-64E5671A313D 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 = K M C _ S C A L E t u n e d K M C t u n e d × 163 24 × 2 13 500 768 500 500 768 768= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned× 163 24 × 2 13 163 163 24 × 2 13 24× 2 13 2 2 13 13 Simplifying, we get: Simplifying, we get: 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276 = K M C _ S C A L E t u n e d K M C t u n e d 785.276= K M C _ S C A L E t u n e d K M C t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E t u n e d K M C _ S C A L E KMC_SCALE t u n e d tuned K M C t u n e d K M C t u n e d K M C KMC t u n e d tuned The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices: The final step is to choose KMC_SCALEtuned such that KMCtunedhas the highest precision within limits (0 to 255). The following table illustrates the possible choices:tunedtuned Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Selection Example for KMC_SCALE Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment Bit KMC_SCALEtuned value KMC_SCALEtuned / 785.276(Actual Value) KMCtuned (Rounded Value) Comment BitKMC_SCALEtuned valuetunedKMC_SCALEtuned / 785.276(Actual Value) tuned(Actual Value)KMCtuned (Rounded Value) tuned(Rounded Value)Comment 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 00b 24 x 28 7.82 8 Avoid selecting, since low precision. 00b24 x 28 87.828Avoid selecting, since low precision. 01b 24 x 29 15.64 16 Avoid selecting, since low precision. 01b24 x 29 915.6416Avoid selecting, since low precision. 10b 24 x 212 125.18 125 Avoid selecting, since low precision. 10b24 x 212 12125.18125Avoid selecting, since low precision. 11b 24 x 213 250.36 250 Can seleect this value, since highest precision. 11b 11b 24 x 213 24 x 213 13 250.36 250.36 250 250 Can seleect this value, since highest precision. Can seleect this value, since highest precision. Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Advanced Parameters Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Filter Constants This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. This section describes how to tune the two filter constants: FLT_K and FLT_GAIN_SEL. FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_GAIN_SEL Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . Denoted by FLT_GAIN_SEL, this parameter selects the gain for the band pass filter. The gain scales the magnitude of current ripples for ease of detection and algorithmic calculation by the Ripple Counter. Recommended to set this to the maximum value (11b) to utilize the full signal range. Settings are as shown in . FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 FLT_K Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples. Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b. Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Denoted by FLT_K, this parameter represents the quality factor or Q-factor of the band pass filter. Tune this parameter to increase or decrease the bandwidth to accommodate a wider or narrower range of ripple frequencies around the center frequency. Center frequency of the filter is based on the frequency estimation of the motor for the ripples.Settings are shown in #GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47. Recommended value is the default value: 0110b.#GUID-5AA53EA7-990E-4A3C-BBBB-1E404ACAB5E9/GUID-B881A102-FB40-403A-8F36-10E08CB6BD47 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Settings for FLT_K Bit Decimal Value 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 Bit Decimal Value Bit Decimal Value BitDecimalValue 0000 0 0.007813 0001 1 0.015265 0010 2 0.03125 0011 3 0.0625 0100 4 0.125 0101 5 0.25 0110 6 0.5 0111 7 0.625 1000 8 0.75 1001 9 0.825 1010 - 1111 10-15 1 0000 0 0.007813 000000.007813 0001 1 0.015265 000110.015265 0010 2 0.03125 001020.03125 0011 3 0.0625 001130.0625 0100 4 0.125 010040.125 0101 5 0.25 010150.25 0110 6 0.5 011060.5 0111 7 0.625 011170.625 1000 8 0.75 100080.75 1001 9 0.825 100190.825 1010 - 1111 10-15 1 1010 - 111110-151 T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. T_MECH_FLT This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter. Tune this parameter to match the inertia of the entire mechanical system. This can be done by observing the ripple counter response during dynamic speed events such as inrush or transient loading. Increasing the value of this parameter slows down the ripple counter response time; decreasing the value speeds up the response time. Setting this parameter to the default value (100b) is recommended since that suffices for most mechanical systems. VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). VSNS_SEL This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b). This parameter is used to select the motor voltage output filtering method (analog or digital) during PWM. The analog filter (0b) filters out the noise based on the voltage difference between the output pins. The digital filter (1b) multiplies the PWM duty cycle with VM to render an average output voltage. Settings are shown in . When analog filter is selected, the cut-off frequency can be selected using the OUT_FLT register. Recommended setting is the analog filter (0b).OUT_FLT Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Additional Error Corrector Parameters This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. This section describes two additional parameters, EC_FALSE_PER and EC_MISS_PER. Please note that these are advanced parameters used for fine tuning the error corrector and used only in extreme scenarios. The default settings work in most cases. EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_FALSE_PER s a 2-bit register that allows the user to select a blanking time window after a current ripple is detected. During this time window, the error corrector classifies any passed ripples from the digital filter as extra ripples and does not count them. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_FALSE_PERafter#GUID-7F3EB7D4-F450-45C8-8BEC-074FDA5776F5/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_FALSE_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PER EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D: Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% EC_MISS_PERis a 2-bit register that allows the user to select a time window for when a current ripple is expected to be detected. During this time window, the error corrector identifies any ripples filtered out from the digital filter to classify them as missed and adds them manually. The time window is represented as a percentage of time between two successive expected current ripples. During this time window, the error corrector takes action if an expected ripple from the digital filter does not arrive. The time window is represented as a percentage of time between two successive expected current ripples. The settings are shown in #GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D:EC_MISS_PERexpected#GUID-4B4EA437-341F-4059-92C0-638EF776EDFB/GUID-F806B92C-CAD8-4D6B-84F1-412B039EA85D Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Settings for EC_MISS_PER Bit Value 00b 20% 01b 30% 10b 40% 11b 50% Bit Value Bit Value BitValue 00b 20% 01b 30% 10b 40% 11b 50% 00b 20% 00b20% 01b 30% 01b30% 10b 40% 10b40% 11b 50% 11b50% Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8234 can help to limit these large currents. Additionally, DRV8234's soft-start feature can be used to limit the inrush current by ramping the PWM duty cycle during startup time. Alternatively, the microcontroller may limit the inrush current via a similar procedure. Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Application Curves Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Example Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Steady State Operation at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 V RC_OUT denotes the pulse train output of the RC_OUT pin Soft Stop at VM = 12 VRC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full Profile RC_OUT denotes the pulse train output of the RC_OUT pin Transient Loading Conditions - Full ProfileRC_OUT denotes the pulse train output of the RC_OUT pin Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8234 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotifications Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. Revision History DATE REVISION NOTES January 2023 * Initial Release Revision History DATE REVISION NOTES January 2023 * Initial Release DATE REVISION NOTES January 2023 * Initial Release DATE REVISION NOTES January 2023 * Initial Release DATE REVISION NOTES January 2023 * Initial Release DATE REVISION NOTES DATE REVISION NOTES DATEREVISIONNOTES January 2023 * Initial Release January 2023 * Initial Release January 2023 January 2023*Initial Release IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. 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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.TI’s Terms of Saleti.com TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated.
6-4T_MECH_FLTR/W4h This parameter determines the cut-off frequency of a low pass filter at the output of the ripple counter to control the response time of the ripple counter to match the intertia of the mechanical system.
Increase this value to for a slower response and decrease it for a faster response.
3-2EC_FALSE_PERR/W1h Sets the window during which the error corrector classifies a current ripple as an extra ripple.
00b: 20%
01b: 30%
10b: 40%
11b: 50%
1-0EC_MISS_PERR/W1h Sets the window during which the error corrector adds a missed ripple.
00b: 20%
01b: 30%
10b: 40%
11b: 50%

7.6.3.11 RC_CTRL7 Register (Offset = 18h) [Reset = 21h]

RC_CTRL7 is shown in Table 7-55.

Return to the Summary Table.

Set the proportional constant in PI control loop.

Table 7-55 RC_CTRL7 Register Field Descriptions
BitFieldTypeResetDescription
7-5KP_DIVR/W1h Used to select a division value for calculating the actual proportional constant for the PI control loop.
Actual proportional constant = KP/KP_DIV.
Settings are as follows:
000b: 32
001b: 64
010b: 128
011b: 256
100b: 512
101b: 16
110b: 1
4-0KPR/W1h Represents the PI loop KP constant. This is not the actual proportional constant that is fed into the gain block of the PI control loop. Rather, the actual proportional constant can be calculated using this value of the KP register.
Actual Proportional Constant = KP/KP_DIV.
For example, if actual proportional constant is 0.0625, then KP can be set to 1 (00001b), and KP_DIV can be set to 16 (corresponds to 101b), hence,
Actual proportional constant = 1/16 = 0.0625.

7.6.3.12 RC_CTRL8 Register (Offset = 19h) [Reset = 21h]

RC_CTRL8 is shown in Table 7-56.

Return to the Summary Table.

Set the integral constant in PI control loop.

Table 7-56 RC_CTRL8 Register Field Descriptions
BitFieldTypeResetDescription
7-5KI_DIVR/W1h Used to select a division value for calculating the actual integral constant for the PI control loop.
Actual integral constant = KI/KI_DIV.
Settings are as follows:
000b: 32
001b: 64
010b: 128
011b: 256
100b: 512
101b: 16
110b: 1
4-0KIR/W1h Represents the PI loop KI constant. This is not the actual integral constant that is fed into the gain block of the PI control loop. Rather, the actual integral constant can be calculated using this value of the KI register.
Actual Integral Constant = KI/KI_DIV.
For example, if actual integral constant is 0.90625, then KI can be set to 29 (11101b), and KI_DIV can be set to 32 (corresponds to 000b), hence,
Actual integral constant = 29/32 = 0.90625.