SLOSE50A April 2020 – June 2021
PRODUCTION DATA
The VM pin should be bypassed to PGND using a low-ESR ceramic bypass capacitor with a recommended value of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace or ground plane connection to the device PGND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component can be an electrolytic capacitor.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.022 µF rated for VM is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.22 µF rated for 16 V is recommended. Place this component as close to the pins as possible.
The OUT1 pins (pins 4, 5, 10, 11 for HTSSOP package; pins 3, 6 for QFN package) must be connected together using a thick PCB trace. Similarly, the OUT2 pins (pins 6, 7, 8, 9 for HTSSOP package; pins 4, 5 for QFN package) must be connected together using a thick PCB trace.
Bypass the DVDD pin to ground with a low-ESR ceramic capacitor. A value of 0.47 µF rated for 6.3 V is recommended. Place this bypassing capacitor as close to the pin as possible.
The thermal PAD must be connected to system ground. To drive more than 5A peak current, a heat sink might be required to be placed near the device.