SLOSE50A April   2020  – June 2021

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
      2. 7.3.2 Current Regulation
      3. 7.3.3 Decay Modes
        1. 7.3.3.1 Mixed Decay
        2. 7.3.3.2 Fast Decay
        3. 7.3.3.3 Smart tune Dynamic Decay
        4. 7.3.3.4 Smart tune Ripple Control
        5. 7.3.3.5 Blanking time
      4. 7.3.4 Charge Pump
      5. 7.3.5 Linear Voltage Regulators
      6. 7.3.6 Logic and Quad-Level Pin Diagrams
        1. 7.3.6.1 nFAULT Pin
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.7.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.7.3 Overcurrent Protection (OCP)
        4. 7.3.7.4 Thermal Shutdown (OTSD)
        5.       Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 nSLEEP Reset Pulse
      4.      Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
          1. 8.2.2.1.1 Power Dissipation and Thermal Calculation
          2. 8.2.2.1.2 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Bridge Control

The DRV8256E is controlled using a PH/EN interface. Table 7-2 gives the full H-bridge state. Note that this table does not take into account the current control built into the DRV8256E. Positive current is defined in the direction of OUT1 to OUT2.

Table 7-2 DRV8256E (PH/EN) Control Interface
nSLEEPENPHOUT1OUT2DESCRIPTION
0XXHi-ZHi-ZSleep mode; H-bridge disabled Hi-Z
10XHi-ZHi-ZH-bridge disabled Hi-Z
110LHReverse (current OUT2 to OUT1)
111HLForward (current OUT1 to OUT2)

The DRV8256P is controlled using a PWM interface. Table 7-3 gives the full H-bridge state. Note that this table does not take into account the current control built into the DRV8256P. Positive current is defined in the direction of OUT1 to OUT2.

Table 7-3 DRV8256P (PWM) Control Interface
nSLEEPIN1IN2OUT1OUT2DESCRIPTION
0XXHi-ZHi-ZSleep mode; H-bridge disabled Hi-Z
100LLBrake; low-side slow decay
101LHReverse (current OUT2 to OUT1)
110HLForward (current OUT1 to OUT2)
111HHBrake; high-side slow decay