SLVSGO4
April 2022
DRV8300-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings AUTO
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Diagrams
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Three BLDC Gate Drivers
8.3.1.1
Gate Drive Timings
8.3.1.1.1
Propagation Delay
8.3.1.1.2
Deadtime and Cross-Conduction Prevention
8.3.1.2
Gate Driver Outputs
8.3.2
Pin Diagrams
8.3.3
Gate Driver Protective Circuits
8.3.3.1
VBSTx Undervoltage Lockout (BSTUV)
8.3.3.2
GVDD Undervoltage Lockout (GVDDUV)
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Bootstrap Capacitor and GVDD Capacitor Selection
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Support Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|20
MPDS362A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
SLVSGO4_pm
slvsgo4_oa
7.6
Timing Diagrams
Figure 7-1
Propagation Delay(t
PD
)
Figure 7-2
Propagation Delay Match (t
PD_match
)