• Menu
  • Product
  • Email
  • PDF
  • Order now

  • DRV8300U: 100-V Three-Phase BLDC Gate Driver

    • SLVSGY3A July   2022  – October 2022 DRV8300U

      PRODUCTION DATA  

  • CONTENTS
  • SEARCH
  • DRV8300U: 100-V Three-Phase BLDC Gate Driver
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 Gate Drive Timings
          1. 8.3.1.1.1 Propagation Delay
          2. 8.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 8.3.1.2 Mode (Inverting and non inverting INLx)
      2. 8.3.2 Pin Diagrams
      3. 8.3.3 Gate Driver Protective Circuits
        1. 8.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 8.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Bootstrap Capacitor and GVDD Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PW|20
    • MPDS362A
  • RGE|24
    • MPQF124G
Thermal pad, mechanical data (Package|Pins)
  • RGE|24
    • QFND008AA
Orderable Information
  • slvsgy3a_oa
  • slvsgy3a_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

DRV8300U: 100-V Three-Phase BLDC Gate Driver

1 Features

  • 100-V Three Phase Half-Bridge Gate driver
    • Drives N-Channel MOSFETs (NMOS)
    • Gate Driver Supply (GVDD): 5-20 V
    • MOSFET supply (SHx) support upto 100 V
  • Integrated Bootstrap Diodes (DRV8300UD devices)
  • Supports Inverting and Non-Inverting INLx inputs
  • Bootstrap gate drive architecture
    • 750-mA source current
    • 1.5-A sink current
  • Supports up to 15S battery powered applications
  • Higher BSTUV (8V typ) and GVDDUV (7.6V typ) threshold to support standard MOSFETs
  • Low leakage current on SHx pins (<55 µA)
  • Absolute maximum BSTx voltage upto 125-V
  • Supports negative transients upto -22-V on SHx
  • Built-in cross conduction prevention
  • Adjustable deadtime through DT pin for QFN package variants
  • Fixed deadtime insertion of 200 nS for TSSOP package variants
  • Supports 3.3-V and 5-V logic inputs with 20 V Abs max
  • 4 nS typical propogation delay matching
  • Compact QFN and TSSOP packages
  • Efficient system design with Power Blocks
  • Integrated protection features
    • BST undervoltage lockout (BSTUV)
    • GVDD undervoltage (GVDDUV)

2 Applications

  • E-Bikes, E-Scooters, and E-Mobility
  • Fans, Pumps, and Servo Drives
  • Brushless-DC (BLDC) Motor Modules and PMSM
  • Cordless Garden and Power Tools, Lawnmowers
  • Cordless Vacuum Cleaners
  • Drones, Robotics, and RC Toys
  • Industrial and Logistics Robots

3 Description

DRV8300U is 100-V three half-bridge gate drivers, capable of driving high-side and low-side N-channel power MOSFETs. The DRV8300UD generates the correct gate drive voltages using an integrated bootstrap diode and external capacitor for the high-side MOSFETs. GVDD is used to generate gate drive voltage for the low-side MOSFETs. The Gate Drive architecture supports peak up to 750-mA source and 1.5-A sink currents.

The phase pins SHx is able to tolerate the significant negative voltage transients; while high side gate driver supply BSTx and GHx is able to support to higher positive voltage transients (125-V) abs max voltage which improves robustness of the system. Small propagation delay and delay matching specifications minimize the dead-time requirement which further improves efficiency. Undervoltage protection is provided for both low and high side through GVDD and BST undervoltage lockout.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DRV8300UDPW TSSOP (20) 6.40 mm × 4.40 mm
DRV8300UDIPW TSSOP (20) 6.40 mm × 4.40 mm
DRV8300UDRGE VQFN (24) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-6E3809C3-B1FF-4889-8B6F-03FF9BE4CC85-low.gif Simplified Schematic for DRV8300UD

4 Revision History

Changes from Revision * (July 2022) to Revision A (October 2022)

  • Updated device status to Production DataGo

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale