SLOS842A September 2013 – June 2015 DRV8301-Q1
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DRV8301-Q1 is a gate driver designed to drive a 3-phase BLDC motor in combination with external power MOSFETs. The device provides a high level of integration with three half-bridge gate drivers, two current shunt amplifiers, overcurrent protection, and a step-down buck regulator.
The DRV8301-Q1 gate drivers may not correctly power up if a voltage greater than 8.5 V is present on any SH_X pin when EN_GATE is first brought logic high (device first enabled) after PVDD1 power is applied. This situation should be avoided by ensuring the voltage levels on the SH_X pins are less than 8.5 V when the DRV8301-Q1 is first enabled. After the first successful enable, EN_GATE can be brought low or high regardless of the SH_X pin voltage with no impact to the device operation.
The following design is a common application of the DRV8301-Q1.
DESIGN PARAMETER | REFERENCE | VALUE |
---|---|---|
Supply voltage | PVDD | 24 V |
Motor winding resistance | MR | 0.5 Ω |
Motor winding inductance | ML | 0.28 mH |
Motor poles | MP | 16 poles |
Motor rated RPM | MRPM | 4000 RPM |
Target full-scale current | IMAX | 14 A |
Sense resistor | RSENSE | 0.01 Ω |
MOSFET Qg | Qg | 29 nC |
MOSFET RDS(on) | RDS(on) | 4.7 mΩ |
VDS trip level | OC_ADJ_SET | 0.123 V |
Switching frequency | ƒSW | 45 kHz |
Series gate resistance | RGATE | 10 Ω |
Amplifier reference | VREF | 3.3 V |
Amplifier gain | Gain | 10 V/V |
NAME | PIN 1 | PIN 2 | RECOMMENDED |
---|---|---|---|
RnOCTW | nOCTW | VCC(1) | ≥10 kΩ |
RnFAULT | nFAULT | VCC(1) | ≥10 kΩ |
RDTC | DTC | GND (PowerPAD) | 0 to 150 kΩ (50 ns to 500 ns) |
CGVDD | GVDD | GND (PowerPAD) | 2.2 µF (20%) ceramic, ≥ 16 V |
CCP | CP1 | CP2 | 0.022 µF (20%) ceramic, rated for PVDD1 |
CDVDD | DVDD | AGND | 1 µF (20%) ceramic, ≥ 6.3 V |
CAVDD | AVDD | AGND | 1 µF (20%) ceramic, ≥ 10 V |
CPVDD1 | PVDD1 | GND (PowerPAD) | ≥4.7 µF (20%) ceramic, rated for PVDD1 |
CBST_X | BST_X | SH_X | 0.1 µF (20%) ceramic, ≥ 16 V |
NAME | PIN 1 | PIN 2 | RECOMMENDED |
---|---|---|---|
RRT_CLK | RT_CLK | GND (PowerPAD) | See Buck Converter |
CCOMP | COMP | GND (PowerPAD) | See Buck Converter |
RCCOMP | COMP | GND (PowerPAD) | See Buck Converter |
RVSENSE1 | PH (Filtered) | VSENSE | See Buck Converter |
RVSENSE2 | VSENSE | GND (PowerPAD) | See Buck Converter |
RPWRGD | PWRGD | VCC(1) | ≥ 10 kΩ |
LPH | PH | PH (Filtered) | See Buck Converter |
DPH | PH | GND (PowerPAD) | See Buck Converter |
CPH | PH (Filtered) | GND (PowerPAD) | See Buck Converter |
CBST_BK | BST_BK | PH | See Buck Converter |
CPVDD2 | PVDD2 | GND (PowerPAD) | ≥4.7 µF (20%) ceramic, rated for PVDD2 |
CSS_TR | SS_TR | GND (PowerPAD) | See Buck Converter |
The gate drive supply (GVDD) of the DRV8301-Q1 can deliver up to 30 mA (RMS) of current to the external power MOSFETs. Use Equation 3 to determine the approximate RMS load on the gate drive supply:
Example:
This is a rough approximation only.
The DRV8301-Q1 provides overcurrent protection for the external power MOSFETs through the use of VDS monitors for both the high side and low side MOSFETs. These are intended for protecting the MOSFET in overcurrent conditions and not for precise current regulation.
The overcurrent protection works by monitoring the VDS voltage of the external MOSFET and comparing it against the OC_ADJ_SET register value. If the VDS exceeds the OC_ADJ_SET value the DRV8301-Q1 takes action according to the OC_MODE register.
Example:
MOSFET RDS(on) changes with temperature and this will affect the overcurrent trip level.
The DRV8301-Q1 provides two bidirectional low-side current shunt amplifiers. These can be used to sense a sum of the three half-bridges, two of the half-bridges individually, or in conjunction with an additional shunt amplifier to sense all three half-bridges individually.