The DRV8301 is a gate driver IC for three-phase motor drive applications. The device provides three half-bridge drivers, each capable of driving two N-channel MOSFETs. The DRV8301 supports up to 1.7-A source and 2.3-A peak current capability. The DRV8301 can operate off of a single power supply with a wide range from 6-V to 60-V. The device uses a bootstrap gate driver architecture with trickle charge circuitry to support 100% duty cycle. The DRV8301 uses automatic handshaking when the high-side or low-side MOSFET is switching to prevent flow of current. Integrated VDS sensing of the high-side and low-side MOSFETs is used to protect the external power stage against overcurrent conditions.
The DRV8301 includes two current shunt amplifiers for accurate current measurement. The amplifiers support bidirectional current sensing and provide an adjustable output offset up to 3 V.
The DRV8301 also includes an integrated switching mode buck converter with adjustable output and switching frequency. The buck converter can provide up to 1.5 A to support MCU or additional system power needs.
The SPI provides detailed fault reporting and flexible parameter settings such as gain options for the current shunt amplifiers and slew rate control of the gate drivers.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8301 | HTSSOP (56) | 14.00 mm × 8.10 mm |
Changes from E Revision (October 2015) to F Revision
Changes from D Revision (August 2015) to E Revision
Changes from C Revision (January 2015) to D Revision
Changes from B Revision (August 2013) to C Revision
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
RT_CLK | 1 | I | Resistor timing and external clock for buck regulator. Resistor should connect to GND (PowerPAD™) with very short trace to reduce the potential clock jitter due to noise. |
COMP | 2 | O | Buck error amplifier output and input to the output switch current comparator. |
VSENSE | 3 | I | Buck output voltage sense pin. Inverting node of error amplifier. |
PWRGD | 4 | O | An open-drain output with external pullup resistor required. Asserts low if buck output voltage is low due to thermal shutdown, dropout, overvoltage, or EN_BUCK shut down |
nOCTW | 5 | O | Overcurrent and/or overtemperature warning indicator. This output is open drain with external pullup resistor required. Programmable output mode via SPI registers. |
nFAULT | 6 | O | Fault report indicator. This output is open drain with external pullup resistor required. |
DTC | 7 | I | Dead-time adjustment with external resistor to GND |
nSCS | 8 | I | SPI chip select |
SDI | 9 | I | SPI input |
SDO | 10 | O | SPI output |
SCLK | 11 | I | SPI clock signal |
DC_CAL | 12 | I | When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset calibration can be done through external microcontroller. |
GVDD | 13 | P | Internal gate driver voltage regulator. GVDD cap should connect to GND |
CP1 | 14 | P | Charge pump pin 1, ceramic capacitor should be used between CP1 and CP2 |
CP2 | 15 | P | Charge pump pin 2, ceramic capacitor should be used between CP1 and CP2 |
EN_GATE | 16 | I | Enable gate driver and current shunt amplifiers. Control buck through EN_BUCK pin. |
INH_A | 17 | I | PWM input signal (high side), half-bridge A |
INL_A | 18 | I | PWM input signal (low side), half-bridge A |
INH_B | 19 | I | PWM input signal (high side), half-bridge B |
INL_B | 20 | I | PWM input signal (low side), half-bridge B |
INH_C | 21 | I | PWM input signal (high side), half-bridge C |
INL_C | 22 | I | PWM input signal (low side), half-bridge C |
DVDD | 23 | P | Internal 3.3-V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified to drive external circuitry. |
REF | 24 | I | Reference voltage to set output of shunt amplifiers with a bias voltage which equals to half of the voltage set on this pin. Connect to ADC reference in microcontroller. |
SO1 | 25 | O | Output of current amplifier 1 |
SO2 | 26 | O | Output of current amplifier 2 |
AVDD | 27 | P | Internal 6-V supply voltage, AVDD cap should always be installed and connected to AGND. This is an output, but not specified to drive external circuitry. |
AGND | 28 | P | Analog ground pin. Connect directly to GND (PowerPAD). |
PVDD1 | 29 | P | Power supply pin for gate driver, current shunt amplifier, and SPI communication. PVDD1 is independent of buck power supply, PVDD2. PVDD1 cap should connect to GND |
SP2 | 30 | I | Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best common mode rejection. |
SN2 | 31 | I | Input of current amplifier 2 (connecting to negative input of amplifier). |
SP1 | 32 | I | Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best common mode rejection. |
SN1 | 33 | I | Input of current amplifier 1 (connecting to negative input of amplifier). |
SL_C | 34 | I | Low-Side MOSFET source connection, half-bridge C. Low-side VDS measured between this pin and SH_C. |
GL_C | 35 | O | Gate drive output for low-side MOSFET, half-bridge C |
SH_C | 36 | I | High-side MOSFET source connection, half-bridge C. High-side VDS measured between this pin and PVDD1. |
GH_C | 37 | O | Gate drive output for high-side MOSFET, half-bridge C |
BST_C | 38 | P | Bootstrap cap pin for half-bridge C |
SL_B | 39 | I | Low-side MOSFET source connection, half-bridge B. Low-side VDS measured between this pin and SH_B. |
GL_B | 40 | O | Gate drive output for low-side MOSFET, half-bridge B |
SH_B | 41 | I | High-side MOSFET source connection, half-bridge B. High-side VDS measured between this pin and PVDD1. |
GH_B | 42 | O | Gate drive output for high-side MOSFET, half-bridge B |
BST_B | 43 | P | Bootstrap cap pin for half-bridge B |
SL_A | 44 | I | Low-side MOSFET source connection, half-bridge A. Low-side VDS measured between this pin and SH_A. |
GL_A | 45 | O | Gate drive output for low-side MOSFET, half-bridge A |
SH_A | 46 | I | High-side MOSFET source connection, half-bridge A. High-side VDS measured between this pin and PVDD1. |
GH_A | 47 | O | Gate drive output for high-side MOSFET, half-bridge A |
BST_A | 48 | P | Bootstrap cap pin for half-bridge A |
VDD_SPI | 49 | I | SPI supply pin to support 3.3-V or 5-V logic. Connect to the same supply that the MCU uses for SPI operation. |
PH | 50, 51 | O | The source of the internal high side MOSFET of buck converter |
BST_BK | 52 | P | Bootstrap cap pin for buck converter |
PVDD2 | 53, 54 | P | Power supply pin for buck converter, PVDD2 cap should connect to GND. |
EN_BUCK | 55 | I | Enable buck converter. Internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors |
SS_TR | 56 | I | Buck soft-start and tracking. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. Cap should connect to GND |
GND (PowerPAD) |
57 | P | GND pin. The exposed power pad must be electrically connected to ground plane through soldering to PCB for proper operation and connected to bottom side of PCB through vias for better thermal spreading. |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VPVDD1 | DC supply voltage PVDD1 for normal operation | Relative to PGND | 6 | 60 | V |
VPVDD2 | DC supply voltage PVDD2 for buck converter | 3.5 | 60 | V | |
IDIN_EN | Input current of digital pins when EN_GATE is high | 100 | µA | ||
IDIN_DIS | Input current of digital pins when EN_GATE is low | 1 | µA | ||
CO_OPA | Maximum output capacitance on outputs of shunt amplifier | 20 | pF | ||
RDTC | Dead time control resistor range. Time range is 50 ns (-GND) to 500 ns (150 kΩ) with a linear approximation. | 0 | 150 | kΩ | |
IFAULT | nFAULT pin sink current, open-drain | V = 0.4 V | 2 | mA | |
IOCTW | nFAULT pin sink current, open-drain | V = 0.4 V | 2 | mA | |
VREF | External voltage reference voltage for current shunt amplifiers | 2 | 6 | V | |
ƒgate | Operating switching frequency of gate driver | Qg(TOT) = 25 nC or total 30-mA gate drive average current | 200 | kHz | |
Igate | Total average gate drive current | 30 | mA | ||
TA | Ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | DRV8301 | UNIT | |
---|---|---|---|
DCA (HTSSOP) | |||
56 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 30.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 33.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 17.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 7.2 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.9 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT PINS: INH_X, INL_X, nSCS, SDI, SCLK, EN_GATE, DC_CAL | ||||||
VIH | High input threshold | 2 | V | |||
VIL | Low input threshold | 0.8 | V | |||
RPULL_DOWN – INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTS | ||||||
REN_GATE | Internal pulldown resistor for EN_GATE | 100 | kΩ | |||
RINH_X | Internal pulldown resistor for high-side PWMs (INH_A, INH_B, and INH_C) | EN_GATE high | 100 | kΩ | ||
RINH_X | Internal pulldown resistor for low-side PWMs (INL_A, INL_B, and INL_C) | EN_GATE high | 100 | kΩ | ||
RnSCS | Internal pulldown resistor for nSCS | EN_GATE high | 100 | kΩ | ||
RSDI | Internal pulldown resistor for SDI | EN_GATE high | 100 | kΩ | ||
RDC_CAL | Internal pulldown resistor for DC_CAL | EN_GATE high | 100 | kΩ | ||
RSCLK | Internal pulldown resistor for SCLK | EN_GATE high | 100 | kΩ | ||
OUTPUT PINS: nFAULT AND nOCTW | ||||||
VOL | Low output threshold | IO = 2 mA | 0.4 | V | ||
VOH | High output threshold | External 47 kΩ pullup resistor connected to 3-5.5 V | 2.4 | V | ||
IOH | Leakage Current on Open-Drain Pins When Logic High nFAULT and nOCTW) | 1 | µA | |||
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C | ||||||
VGX_NORM | Gate driver Vgs voltage | PVDD = 8 to 60 V, Igate = 30 mA, CCP = 22 nF |
9.5 | 11.5 | V | |
PVDD = 8 to 60 V, Igate = 30 mA, CCP = 220 nF |
9.5 | 11.5 | ||||
VGX_MIN | Gate driver Vgs voltage | PVDD = 6 to 8 V, Igate = 15 mA, CCP = 22 nF |
8.8 | V | ||
PVDD = 6 to 8 V, Igate = 30 mA, CCP = 220 nF |
8.3 | |||||
Ioso1 | Maximum source current setting 1, peak | Vgs of FET equals to 2 V. REG 0x02 | 1.7 | A | ||
Iosi1 | Maximum sink current setting 1, peak | Vgs of FET equals to 8 V. REG 0x02 | 2.3 | A | ||
Ioso2 | Source current setting 2, peak | Vgs of FET equals to 2 V. REG 0x02 | 0.7 | A | ||
Iosi2 | Sink current setting 2, peak | Vgs of FET equals to 8 V. REG 0x02 | 1 | A | ||
Ioso3 | Source current setting 3, peak | Vgs of FET equals to 2 V. REG 0x02 | 0.25 | A | ||
Iosi3 | Sink current setting 3, peak | Vgs of FET equals to 8 V. REG 0x02 | 0.5 | A | ||
Rgate_off | Gate output impedence during standby mode when EN_GATE low (pins GH_x, GL_x) | 1.6 | 2.4 | kΩ | ||
SUPPLY CURRENTS | ||||||
IPVDD1_STB | PVDD1 supply current, standby | EN_GATE is low. PVDD1 = 8 V. | 20 | 50 | µA | |
IPVDD1_OP | PVDD1 supply current, operating | EN_GATE is high, no load on gate drive output, switching at 10 kHz, 100 nC gate charge |
15 | mA | ||
IPVDD1_HIZ | PVDD1 Supply current, Hi-Z | EN_GATE is high, gate not switching | 2 | 5 | 10 | mA |
INTERNAL REGULATOR VOLTAGE | ||||||
AVDD | AVDD voltage | PVDD = 8 to 60 V | 6 | 6.5 | 7 | V |
PVDD = 6 to 60 V | 5.5 | 6 | ||||
DVDD | DVDD voltage | 3 | 3.3 | 3.6 | V | |
VOLTAGE PROTECTION | ||||||
VPVDD_UV | Undervoltage protection limit, PVDD | PVDD falling | 5.9 | V | ||
PVDD rising | 6 | |||||
VGVDD_UV | Undervoltage protection limit, GVDD | GVDD falling | 8 | V | ||
VGVDD_OV | Overvoltage protection limit, GVDD | 16 | V | |||
CURRENT PROTECTION, (VDS SENSING) | ||||||
VDS_OC | Drain-source voltage protection limit | PVDD = 8 to 60 V | 0.125 | 2.4 | V | |
PVDD = 6 to 8 V(1) | 0.125 | 1.491 | ||||
Toc | OC sensing response time | 1.5 | µs | |||
TOC_PULSE | nOCTW pin reporting pulse stretch length for OC event | 64 | µs | |||
TEMPERATURE PROTECTION | ||||||
OTW_CLR | Junction temperature for resetting overtemperature warning | 115 | °C | |||
OTW_SET/OTSD_CLR | Junction temperature for overtemperature warning and resetting over temperature shut down | 130 | °C | |||
OTSD_SET | Junction temperature for overtemperature shut down | 150 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
G1 | Gain option 1 | TC = –40°C to 125°C | 9.5 | 10 | 10.5 | V/V |
G2 | Gain option 2 | TC = –40°C to 125°C | 18 | 20 | 21 | V/V |
G3 | Gain Option 3 | TC = –40°C to 125°C | 38 | 40 | 42 | V/V |
G4 | Gain Option 4 | TC = –40°C to 125°C | 75 | 80 | 85 | V/V |
tsettling | Settling time to 1% | TC = 0 to 60°C, G = 10, Vstep = 2 V | 300 | ns | ||
tsettling | Settling time to 1% | TC = 0 to 60°C, G = 20, Vstep = 2 V | 600 | ns | ||
tsettling | Settling time to 1% | TC = 0 to 60°C, G = 40, Vstep = 2 V | 1.2 | µs | ||
tsettling | Settling time to 1% | TC = 0 to 60°C, G = 80, Vstep = 2 V | 2.4 | µs | ||
Vswing | Output swing linear range | 0.3 | 5.7 | V | ||
Slew rate | G = 10 | 10 | V/µs | |||
DC_offset | Offset error RTI | G = 10 with input shorted | 4 | mV | ||
Drift_offset | Offset drift RTI | 10 | µV/C | |||
Ibias | Input bias current | 100 | µA | |||
Vin_com | Common input mode range | –0.15 | 0.15 | V | ||
Vin_dif | Differential input range | –0.3 | 0.3 | V | ||
Vo_bias | Output bias | With zero input current, Vref up to 6 V | –0.5% | 0.5 × Vref | 0.5% | V |
CMRR_OV | Overall CMRR with gain resistor mismatch | CMRR at DC, gain = 10 | 70 | 85 | dB |
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
tSPI_READY | SPI ready after EN_GATE transitions to HIGH | PVDD > 6 V | 5 | 10 | ms | |
tCLK | Minimum SPI clock period | 100 | ns | |||
tCLKH | Clock high time | See Figure 1 | 40 | |||
tCLKL | Clock low time | See Figure 1 | 40 | |||
tSU_SDI | SDI input data setup time | 20 | ns | |||
tHD_SDI | SDI input data hold time | 30 | ns | |||
tD_SDO | SDO output data delay time, CLK high to SDO valid | CL = 20 pF | 20 | ns | ||
tHD_SDO | SDO output data hold time | See Figure 1 | 40 | |||
tSU_SCS | SCS setup time | See Figure 1 | 50 | ns | ||
tHD_SCS | SCS hold time | 50 | ns | |||
tHI_SCS | SCS minimum high time before SCS active low | 40 | ns | |||
tACC | SCS access time, SCS low to SDO out of high impedance | 10 | ns | |||
tDIS | SCS disable time, SCS high to SDO high impedance | 10 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
TIMING, OUTPUT PINS | ||||||
tpd,If-O | Positive input falling to GH_x falling | CL = 1 nF, 50% to 50% | 45 | ns | ||
tpd,Ir-O | Positive input rising to GL_x falling | CL = 1 nF, 50% to 50% | 45 | ns | ||
td_min | Minimum dead time after hand shaking(1) | 50 | ns | |||
tdtp | Dead time | With RDTC set to different values | 50 | 500 | ns | |
tGDr | Rise time, gate drive output | CL = 1 nF, 10% to 90% | 25 | ns | ||
tGDF | Fall time, gate drive output | CL = 1 nF, 90% to 10% | 25 | ns | ||
tON_MIN | Minimum on pulse | Not including handshake communication. Hi-Z to on state, output of gate driver | 50 | ns | ||
tpd_match | Propagation delay matching between high side and low side | 5 | ns | |||
tdt_match | Deadtime matching | 5 | ns | |||
TIMING, PROTECTION, AND CONTROL | ||||||
tpd,R_GATE-OP | Start-up time, from EN_GATE active high to device ready for normal operation | PVDD is up before start-up, all charge pump caps and regulator caps as in recommended condition | 5 | 10 | ms | |
tpd,R_GATE-Quick | If EN_GATE goes from high to low and back to high state within quick reset time, it will only reset all faults and gate driver without powering down charge pump, current amp, and related internal voltage regulators. | Maximum low pulse time | 10 | µs | ||
tpd,E-L | Delay, error event to all gates low | 200 | ns | |||
tpd,E-FAULT | Delay, error event to nFAULT low | 200 | ns |