SLOS719F August   2011  – January 2016 DRV8301

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Current Shunt Amplifier Characteristics
    6. 6.6 Buck Converter Characteristics
    7. 6.7 SPI Timing Requirements (Slave Mode Only)
    8. 6.8 Gate Timing and Protection Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three-Phase Gate Driver
      2. 7.3.2 Current Shunt Amplifiers
      3. 7.3.3 Buck Converter
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Overcurrent Protection and Reporting (OCP)
        2. 7.3.4.2 Undervoltage Protection (PVDD_UV and GVDD_UV)
        3. 7.3.4.3 Overvoltage Protection (GVDD_OV)
        4. 7.3.4.4 Overtemperature Protection
        5. 7.3.4.5 Fault and Protection Handling
      5. 7.3.5 Start-up and Shutdown Sequence Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN_GATE
      2. 7.4.2 DTC
      3. 7.4.3 VDD_SPI
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Read / Write Bit
      2. 7.6.2 Address Bits
      3. 7.6.3 SPI Data Bits
        1. 7.6.3.1 Status Registers
        2. 7.6.3.2 Control Registers
        3. 7.6.3.3 Overcurrent Adjustment
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Gate Driver Power-Up Sequencing Errata
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current Load
        2. 8.2.2.2 Overcurrent Protection Setup
        3. 8.2.2.3 Sense Amplifier Setup
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DCA Package
56-Pin HTSSOP with PowerPAD™
Top View
DRV8301 po_los719.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
RT_CLK 1 I Resistor timing and external clock for buck regulator. Resistor should connect to GND (PowerPAD™) with very short trace to reduce the potential clock jitter due to noise.
COMP 2 O Buck error amplifier output and input to the output switch current comparator.
VSENSE 3 I Buck output voltage sense pin. Inverting node of error amplifier.
PWRGD 4 O An open-drain output with external pullup resistor required. Asserts low if buck output voltage is low due to thermal shutdown, dropout, overvoltage, or EN_BUCK shut down
nOCTW 5 O Overcurrent and/or overtemperature warning indicator. This output is open drain with external pullup resistor required. Programmable output mode via SPI registers.
nFAULT 6 O Fault report indicator. This output is open drain with external pullup resistor required.
DTC 7 I Dead-time adjustment with external resistor to GND
nSCS 8 I SPI chip select
SDI 9 I SPI input
SDO 10 O SPI output
SCLK 11 I SPI clock signal
DC_CAL 12 I When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset calibration can be done through external microcontroller.
GVDD 13 P Internal gate driver voltage regulator. GVDD cap should connect to GND
CP1 14 P Charge pump pin 1, ceramic capacitor should be used between CP1 and CP2
CP2 15 P Charge pump pin 2, ceramic capacitor should be used between CP1 and CP2
EN_GATE 16 I Enable gate driver and current shunt amplifiers. Control buck through EN_BUCK pin.
INH_A 17 I PWM input signal (high side), half-bridge A
INL_A 18 I PWM input signal (low side), half-bridge A
INH_B 19 I PWM input signal (high side), half-bridge B
INL_B 20 I PWM input signal (low side), half-bridge B
INH_C 21 I PWM input signal (high side), half-bridge C
INL_C 22 I PWM input signal (low side), half-bridge C
DVDD 23 P Internal 3.3-V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified to drive external circuitry.
REF 24 I Reference voltage to set output of shunt amplifiers with a bias voltage which equals to half of the voltage set on this pin. Connect to ADC reference in microcontroller.
SO1 25 O Output of current amplifier 1
SO2 26 O Output of current amplifier 2
AVDD 27 P Internal 6-V supply voltage, AVDD cap should always be installed and connected to AGND. This is an output, but not specified to drive external circuitry.
AGND 28 P Analog ground pin. Connect directly to GND (PowerPAD).
PVDD1 29 P Power supply pin for gate driver, current shunt amplifier, and SPI communication. PVDD1 is independent of buck power supply, PVDD2. PVDD1 cap should connect to GND
SP2 30 I Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best common mode rejection.
SN2 31 I Input of current amplifier 2 (connecting to negative input of amplifier).
SP1 32 I Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best common mode rejection.
SN1 33 I Input of current amplifier 1 (connecting to negative input of amplifier).
SL_C 34 I Low-Side MOSFET source connection, half-bridge C. Low-side VDS measured between this pin and SH_C.
GL_C 35 O Gate drive output for low-side MOSFET, half-bridge C
SH_C 36 I High-side MOSFET source connection, half-bridge C. High-side VDS measured between this pin and PVDD1.
GH_C 37 O Gate drive output for high-side MOSFET, half-bridge C
BST_C 38 P Bootstrap cap pin for half-bridge C
SL_B 39 I Low-side MOSFET source connection, half-bridge B. Low-side VDS measured between this pin and SH_B.
GL_B 40 O Gate drive output for low-side MOSFET, half-bridge B
SH_B 41 I High-side MOSFET source connection, half-bridge B. High-side VDS measured between this pin and PVDD1.
GH_B 42 O Gate drive output for high-side MOSFET, half-bridge B
BST_B 43 P Bootstrap cap pin for half-bridge B
SL_A 44 I Low-side MOSFET source connection, half-bridge A. Low-side VDS measured between this pin and SH_A.
GL_A 45 O Gate drive output for low-side MOSFET, half-bridge A
SH_A 46 I High-side MOSFET source connection, half-bridge A. High-side VDS measured between this pin and PVDD1.
GH_A 47 O Gate drive output for high-side MOSFET, half-bridge A
BST_A 48 P Bootstrap cap pin for half-bridge A
VDD_SPI 49 I SPI supply pin to support 3.3-V or 5-V logic. Connect to the same supply that the MCU uses for SPI operation.
PH 50, 51 O The source of the internal high side MOSFET of buck converter
BST_BK 52 P Bootstrap cap pin for buck converter
PVDD2 53, 54 P Power supply pin for buck converter, PVDD2 cap should connect to GND.
EN_BUCK 55 I Enable buck converter. Internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors
SS_TR 56 I Buck soft-start and tracking. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. Cap should connect to GND
GND
(PowerPAD)		 57 P GND pin. The exposed power pad must be electrically connected to ground plane through soldering to PCB for proper operation and connected to bottom side of PCB through vias for better thermal spreading.
(1) KEY: I =Input, O = Output, P = Power